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DATA SHEET
MOS INTEGRATED CIRCUIT
PD17010
4-BIT SINGLE-CHIP MICROCONTROLLER WITH HARDWARE DEDICATED TO DIGITAL TUNING SYSTEM
The PD17010 is a 4-bit single-chip CMOS microcontroller containing hardware for digital tuning systems. The CPU uses a 17K architecture and can directly manipulate the data memory and control various operations and peripheral hardware with a single instruction. All instructions are 16-bit 1-word instructions. As the peripheral hardware, a prescaler for digital tuning that operates at up to 150 MHz, PLL frequency synthesizer, and frequency counter, as well as many I/O ports, LCD controller/driver, 12-bit timer, A/D converter, D/A converter (PWM output), clock generator port are provided. Therefore, a high-performance digital tuning system with sophisticated functions can be configured with a single chip. The PD17P010 is available as a one-time PROM model of the PD17010. This one-time PROM model can be used for evaluation of the program of the PD17010 and small-scale production of the application system.
FEATURES * 17K architecture: General-purpose register
system
* A variety of peripheral hardware
General-purpose I/O ports, LCD controller/driver, serial interface, 12-bit timer, A/D converter, D/A converter (PWM output), clock generator port, frequency counter
* Program memory (ROM)
16K bytes (7932 x 16 bits)
* General-purpose data memory (RAM)
432 x 4 bits
* Many interrupts
External: 1 Internal: 4 External/internal (multiplexed): 1
* Instruction execution time
4.44 s (with 4.5-MHz crystal resonator)
* Decimal operation * Table reference * Hardware for PLL frequency synthesizer
Dual modulus prescaler (150 MHz MAX.), programmable divider, phase comparator, charge pump
* Power-ON reset, reset by CE pin, and power failure detection circuit * Low power-dissipation CMOS * Supply voltage: 5 V10 %
The information in this document is subject to change without notice. Document No. U10340EJ2V0DS00 (2nd edition) (Previous No. ID-2878) Date Published October 1995 P Printed in Japan
(c)
1991
PD17010
ORDERING INFORMATION
Part Number Package 80-pin plastic QFP (14 x 20 mm) 80-pin plastic QFP (14 x 20 mm)
PD17010GF-xxx-3B9 PD17010GF-Exx-3B9Note
Note
Model supporting I2C bus. To use the I2C bus (including when the function is implemented by program without using the peripheral hardware), consult NEC when ordering mask.
Remark xxx indicates a ROM code.
FUNCTIONAL OUTLINE
Item Program memory (ROM) * 16K bytes (7932 x 16 bits) All internal ROM areas can be referenced through table General-purpose data memory (RAM) * 432 x 4 bits Data buffer : 4 x 4 bits, general register : 16 x 4 bits System register Register file General-purpose port register (including LCD dot data register) Instruction execution time Stack level General-purpose ports * 4.44 s (with 4.5-MHz crystal resonator) * 9 levels (stack can be manipulated) * I/O ports : 16 * Input ports : 8 * Output ports : 9 (+30: LCD segment pin) Clock generator port (CGP) *1 VDP (Variable Duty Pulse) and SG (Signal Generator) functions LCD controller/driver * 30 segments, 2 commons 1/2 duty, 1/2 bias, frame frequency: 250 MHz, drive voltage: VDD Segment pins multiplexed with key source: 16 All 30 pins can be used as output port pins (4, 4, 6, and 16 pins can be independently set) Serial interface * 2 systems (3 channels) Serial interface 0 : 2-line (I2C bus, serial I/O) 3-line (serial I/O) Serial interface 1 : 3-line (serial I/O) D/A converter A/D converter * 8 bits x 3 (PWM output, output voltage: 16 V MAX.) * 6 bits x 6 (successive approximation via software) * 12 x 4 bits * 41 x 4 bits (control register) * 24 x 4 bits Function
2
PD17010
Item Interrupt * 6 (maskable interrupts) External : 1 (INT0 pin)
Function
Internal : 4 (12-bit timer, basic timer 1, serial interface 0, frequency counter) External/internal (multiplexed) : 1 (INT1 pin or overflow of timer/counter) Timer * 3 channels 12-bit timer (1, 50 s) Basic timer 0 carry (1, 5, 100, 250 ms) Basic timer 1 interrupt (1, 5, 100, 250 ms) Reset * Power-ON reset (on power up) * Reset by CE pin (CE pin low level high level) * Power failure detection function PLL frequency synthesizer Division method * 2 types Direct division (VCOL pin: 30 MHz MAX.) Pulse swallow (VCOL pin: 40 MHz MAX.) (VCOH pin: 150 MHz MAX.) Reference frequency * 12 types selectable by program 1, 1.25, 2.5, 3, 5, 6.25, 9, 10, 12.5, 25, 50, 100 kHz Charge pump Phase comparator * Two independent error out outputs * Unlock detection programmable Delay time of unlock F/F selectable Frequency counter * Frequency measurement P1D3/FMIFC pin : 5 to 15 MHz P1D2/AMIFC pin : 0.1 to 1 MHz * External gate width measurement P1A0/FCG pin Supply voltage Package 5 V 10 % 80-pin plastic QFP (14 x 20 mm)
3
PD17010
PIN CONFIGURATION (Top View)
LCD0/P0Y0/KS0 LCD1/P0Y1/KS1 LCD2/P0Y2/KS2 LCD3/P0Y3/KS3 LCD4/P0Y4/KS4 LCD5/P0Y5/KS5 LCD6/P0Y6/KS6 LCD7/P0Y7/KS7 LCD8/P0Y8/KS8 LCD9/P0Y9/KS9
P0D0/ADC2
P0D1/ADC3
P0D2/ADC4
P0C1 P0C0 P0A3/SDA P0A2/SCL P0A1/SCK0 P0A0/SO0 P0B3/SI0 P0B2/SCK1 P0B1/SO1 P0B0/SI1 INT1 INT0 CE P1A3 P1A2 P1A1 PIA0/FCG PIB3/PWM2 PIB2/PWM1 PIB1/PWM0 PIB0/CGP P1C3 P1C2 P1C1
1 2 3 4 5 6 7 8 9
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56
P0D3/ADC5
P0C2
P0C3
LCD10/P0Y10/KS10 LCD11/P0Y11/KS11 LCD12/P0Y12/KS12 LCD13/P0Y13/KS13 LCD14/P0Y14/KS14 LCD15/P0Y15/KS15 LCD16/P0X0 LCD17/P0X1 LCD18/P0X2 LCD19/P0X3 LCD20/P0X4 LCD21/P0X5 LCD22/P0E0 LCD23/P0E1 LCD24/P0E2 LCD25/P0E3 LCD26/P0F0 LCD27/P0F1 LCD28/P0F2 LCD29/P0F3 COM0 COM1 P2A0 VDD2
10 11 12 13 14 15 16 17 18 19 20 21 22 23
PD17010GF-xxx-3B9 PD17010GF-Exx-3B9
55 54 53 52 51 50 49 48 47 46 45 44 43 42
24 41 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
P1D3/FMIFC
P1D2/AMIFC
P1D1/ADC1
P1D0/ADC0
VCOL
VCOH
GND
P1C0
XOUT
VDD1
EO0
EO1
XIN
NC
NC
4
NC
PD17010
PIN NAME
ADC0-ADC5 AMIFC CE CGP EO0, EO1 FCG FMIFC GND INT0, INT1 KS0-KS15 LCD0-LCD29 NC P0A0-P0A3 P0B0-P0B3 P0C0-P0C3 P0D0-P0D3 P0E0-P0E3 : : : : : : : : : : : : : : : : : A/D converter input AM intermediate frequency counter input Chip enable input Clock generator port LCD common signal output Error out output Frequency count input for external gate FM intermediate frequency counter input Ground External interrupt input Key source signal output LCD segment signal output No connection Port 0A Port 0B Port 0C Port 0D Port 0E P0F0-P0F3 P0X0-P0X5 P0Y0-P0Y15 P1A0-P1A3 P1B0-P1B3 P1C0-P1C3 P1D0-P1D3 P2A0 SCK0, SCK1 SCL SDA SI0, SI1 SO0, SO1 VCOH VCOL VDD1, VDD2 XIN, XOUT : : : : : : : : : : : : : : : : : Port 0F Port 0X Port 0Y Port 1A Port 1B Port 1C Port 1D Port 2A D/A converter output Serial clock I/O Serial clock I/O Serial data I/O Serial data input Serial data output Local oscillation input Local oscillation input Power supply Crystal resonator connection
COM0, COM1 :
PWM0-PWM2 :
5
PD17010
BLOCK DIAGRAM
FCG (P1A0) P0A0-P0A3 P0B0-P0B3 P0C0-P0C3 P0D0-P0D3 P1A0-P1A3 P1B0-P1B3 P1C0-P1C3 P1D0-P1D3 P2A0 SDA (P0A3) P0E0-P0E3 P0F0-P0F3 P0X0-P0X5 P0Y0-P0Y15 4 SCL (P0A2) 4 6 16 Instruction Decoder Serial Interface 0 SCK0 (P0A1) SO0 (P0A0) SI0 (P0B3) SCK1 (P0B2) COM0 COM1 LCD0 (P0Y0/KS0) LCD15 (P0Y15/KS15) LCD16 (P0X0) LCD21 (P0X5) LCD22 (P0E0) LCD25 (P0E3) LCD26 (P0F0) LCD29 (P0F3) VCOH VCOL EO0 EO1 PLL Basic Timer 1 CPU Peripheral Stack 9 x 13 bits 12-bit Timer
LCD Controller /Driver
4 4 RF 4 4 4 4 4 4 ALU Port RAM 432 x 4 bits SYSTEM REG.
Frequency Counter
FMIFC (P1D3) AMIFC (P1D2) ADC5 (P0D3)
A/D Converter
ADC2 (P0D0) ADC1 (P1D1) ADC0 (P1D0)
D/A Converter
PWM2 (P1B3) PWM0 (P1B1)
CGP
CGP (P1B0)
ROM 7932 x 16 bits
Serial Interface 1
SO1 (P0B1) SI1 (P0B0)
Program Counter
Interrupt Control
INT0 INT1
Basic Timer 0
XIN XOUT
OSC
VDD1 Reset VDD2 CE GND
6
PD17010
CONTENTS
1. PIN FUNCTIONS ............................................................................................................................
1.1 1.2 1.3 1.4 1.5 Pin Function List ................................................................................................................................. Notes on Using General-Purpose Ports ........................................................................................... Equivalent Circuits of Pins ................................................................................................................. Processing of Unused Pins ............................................................................................................... Notes on Using CE, INT0, and INT1 Pins ...........................................................................................
12
12 17 18 23 24
2. PROGRAM MEMORY (ROM) ........................................................................................................
2.1 2.2 2.3 2.4 2.5 Outline of Program Memory ............................................................................................................... Program Memory ................................................................................................................................. Program Counter ................................................................................................................................. Program Flow ...................................................................................................................................... Notes on Using Program Memory .....................................................................................................
25
25 26 26 27 28
3. ADDRESS STACK (ASK) ..............................................................................................................
3.1 3.2 3.3 3.4 3.5 Outline of Address Stack ................................................................................................................... Address Stack Register (ASR) ........................................................................................................... Stack Pointer (SP) ............................................................................................................................... Operation of Address Stack ............................................................................................................... Notes on Using Address Stack ..........................................................................................................
29
29 29 31 32 32
4. DATA MEMORY (RAM) ...................................................................................................................
4.1 4.2 4.3 4.4 Outline of Data Memory ...................................................................................................................... Configuration and Function of Data Memory ................................................................................... Addressing of Data Memory .............................................................................................................. Notes on Using Data Memory ............................................................................................................
33
33 34 36 37
5. SYSTEM REGISTER (SYSREG) ....................................................................................................
5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 Outline of System Register ................................................................................................................ System Register List .......................................................................................................................... Address Register (AR) ........................................................................................................................ Window Register (WR) ........................................................................................................................ Bank Register (BANK) ........................................................................................................................ Index Register (IX) and Data Memory Row Address Pointer (MP: Memory Pointer) ................... General Register Pointer (RP) ........................................................................................................... Program Status Word (PSWORD) ...................................................................................................... Notes on Using System Register ......................................................................................................
38
38 39 40 42 43 44 46 48 49
6. GENERAL REGISTER (GR) ............................................................................................................
6.1 6.2 6.3 6.4 Outline of General Register ............................................................................................................... General Register ................................................................................................................................. General Register Address Generation by Each Instruction ............................................................ Notes on Using General Register ......................................................................................................
50
50 50 51 52
7
PD17010
7. ALU (ARITHMETIC LOGIC UNIT) BLOCK ...................................................................................
7.1 7.2 7.3 7.4 Outline of ALU Block .......................................................................................................................... Configuration and Function of Each Block ...................................................................................... ALU Processing Instruction List ....................................................................................................... Notes on Using ALU ...........................................................................................................................
53
53 54 54 58
8. REGISTER FILE (RF) .....................................................................................................................
8.1 8.2 8.3 8.4 Outline of Register File ....................................................................................................................... Configuration and Function of Register File .................................................................................... Control Registers ................................................................................................................................ Notes on Using Register File .............................................................................................................
59
59 60 61 68
9. DATA BUFFER (DBF) ....................................................................................................................
9.1 9.2 9.3 9.4 Outline of Data Buffer ......................................................................................................................... Data Buffer ........................................................................................................................................... List of Peripheral Hardware and Data Buffer Functions ................................................................. Notes on Using Data Buffer ...............................................................................................................
69
69 70 71 74
10. INTERRUPT ...................................................................................................................................
10.1 10.2 10.3 10.4 10.5 10.6 10.7 10.8 10.9 Outline of Interrupt Block ................................................................................................................... Interrupt Control Block ....................................................................................................................... Interrupt Stack ..................................................................................................................................... Stack Pointer, Address Stack Register, and Program Counter ...................................................... Interrupt Enable Flip-Flop (INTE) ....................................................................................................... Accepting Interrupt ............................................................................................................................. Operation after Accepting Interrupt .................................................................................................. Returning from Interrupt Processing Routine .................................................................................. External (INT0 and INT1 Pins) Interrupts ...........................................................................................
75
75 77 83 85 85 86 90 90 91 93
10.10 Internal Interrupts ...............................................................................................................................
11. TIMER FUNCTION .........................................................................................................................
11.1 11.2 11.3 11.4 11.5 Configuration of Timer ....................................................................................................................... Functional Outline of Timer ............................................................................................................... Basic Timer 0 Carry ............................................................................................................................
95
95 97 97
Basic Timer 1 Interrupt ....................................................................................................................... 113 12-Bit Timer ......................................................................................................................................... 122
12. STANDBY .................................................................................................................................... 136
12.1 12.2 12.3 12.4 12.5 12.6 12.7 Configuration of Standby Block ........................................................................................................ 136 Standby Function ................................................................................................................................ 137 Device Operation Mode Set by CE Pin .............................................................................................. 137 Halt Function ....................................................................................................................................... 139 Clock Stop Function ........................................................................................................................... 150 Device Operation in Halt and Clock Stop Status ............................................................................. 153 Current Dissipation in Halt and Clock Stop Status .......................................................................... 155
8
PD17010
13. RESET ........................................................................................................................................... 160
13.1 13.2 13.3 13.4 13.5 13.6 Configuration of Reset Block ............................................................................................................. 160 Reset Function .................................................................................................................................... 161 CE Reset .............................................................................................................................................. 162 Power-ON Reset .................................................................................................................................. 167 Relation between CE Reset and Power-ON Reset ........................................................................... 170 Power Failure Detection ..................................................................................................................... 174
14. PLL FREQUENCY SYNTHESIZER ............................................................................................... 182
14.1 14.2 14.3 14.4 14.5 14.6 14.7 14.8 Configuration of PLL Frequency Synthesizer .................................................................................. 182 Functional Outline of PLL Frequency Synthesizer .......................................................................... 183 Input Selector Block and Programmable Divider ............................................................................ 184 Reference Frequency Generator ....................................................................................................... 189 Phase Comparator (-DET), Charge Pump, and Unlock Detection Block ..................................... 191 PLL Disabled Status ........................................................................................................................... 195 Using PLL Frequency Synthesizer .................................................................................................... 196 Status on Reset ................................................................................................................................... 199
15. GENERAL-PURPOSE PORTS ...................................................................................................... 200
15.1 15.2 15.3 15.4 15.5 15.6 Configuration and Classification of General-Purpose Ports .......................................................... 200 Functional Outline of General-Purpose Ports .................................................................................. 202 General-Purpose I/O Ports (P0A, P0B, P0C, and P1A) ................................................................... 207 General-Purpose Input Ports (P0D and P1D) ................................................................................... 215 General-Purpose Output Ports (P1B, P1C, and P2A) ...................................................................... 217 General-Purpose Output Ports (P0E, P0F, P0X, and P0Y) ............................................................... 219
16. A/D CONVERTER (ADC) ............................................................................................................... 227
16.1 16.2 16.3 16.4 16.5 16.6 16.7 16.8 16.9 Configuration of A/D Converter ......................................................................................................... 227 Functional Outline of A/D Converter ................................................................................................. 227 Input Select Block ............................................................................................................................... 228 Compare Voltage Generator Block .................................................................................................... 230 Compare Block .................................................................................................................................... 233 Performance of A/D Converter ........................................................................................................... 234 Using A/D Converter ........................................................................................................................... 235 Notes on Using A/D Converter ........................................................................................................... 240 Reset Status ........................................................................................................................................ 240
17. D/A CONVERTER (DAC) ............................................................................................................... 241
17.1 17.2 17.3 17.4 17.5 Configuration of D/A Converter ......................................................................................................... 241 Functional Outline of D/A Converter ................................................................................................. 241 Output Select Block ............................................................................................................................ 242 Duty Setting Block and Clock Generation Block ............................................................................. 244 Reset Status ........................................................................................................................................ 247
18. CLOCK GENERATOR PORT (CGP) ............................................................................................. 248
18.1 18.2 18.3 18.4 Configuration of Clock Generator Port ............................................................................................. 248 Functional Outline of Clock Generator Port ..................................................................................... 248 Output Select Block ............................................................................................................................ 249 VDP/SG Setting Block and Clock Generation Block ....................................................................... 251
9
PD17010
18.5 18.6 18.7 Using Clock Generator ....................................................................................................................... 257 Reset Status ........................................................................................................................................ 258 Notes on Using Clock Generator Port ............................................................................................... 258
19. SERIAL INTERFACE ..................................................................................................................... 260
19.1 19.2 19.3 19.4 19.5 19.6 19.7 19.8 19.9 Configuration of Serial Interface ....................................................................................................... 260 Functional Outline of Serial Interface ............................................................................................... 261 Configuration of Serial Interface 0 (SIO0) ......................................................................................... 262 Functional Outline of Serial Interface 0 ............................................................................................ 264 Shift Clock and Serial Data I/O Pin Control Block ........................................................................... 266 Clock Generation Block ..................................................................................................................... 268 Clock Counter and Start/Stop Detection Block ................................................................................ 273 Presettable Shift Register 0 (SIO0SFR) ............................................................................................ 278 Wait Block and Acknowledge ............................................................................................................ 281
19.10 Interrupt Control Block ....................................................................................................................... 289 19.11 Using Serial Interface 0 ...................................................................................................................... 291 19.12 Reset Status of Serial Interface 0 ...................................................................................................... 319 19.13 Configuration of Serial Interface 1 (SIO1) ......................................................................................... 320 19.14 Functional Outline of Serial Interface 1 ............................................................................................ 321 19.15 Shift Clock and Serial Data I/O Pin Control Block ........................................................................... 322 19.16 Clock Generation Block ..................................................................................................................... 324 19.17 Clock Counter ...................................................................................................................................... 326 19.18 Presettable Shift Register 1 (SIO1SFR) ............................................................................................ 327 19.19 Wait Block ............................................................................................................................................ 330 19.20 Using Serial Interface 1 ...................................................................................................................... 332 19.21 Reset Status of Serial Interface 1 ...................................................................................................... 339
20. FREQUENCY COUNTER (FC) ...................................................................................................... 340
20.1 20.2 20.3 20.4 20.5 20.6 20.7 20.8 Configuration of Frequency Counter ................................................................................................ 340 Functional Outline of IF Counter ....................................................................................................... 340 I/O Select Block and Gate Time Control Block ................................................................................. 342 Start/Stop Control Block and IF Counter .......................................................................................... 345 Using IF Counter Function ................................................................................................................. 353 Using External Gate Counter Function ............................................................................................. 355 Reset Status ........................................................................................................................................ 356 Notes on Using Frequency Counter .................................................................................................. 357
21. LCD CONTROLLER/DRIVER ........................................................................................................ 358
21.1 21.2 21.3 21.4 21.5 21.6 Configuration of LCD Controller/Driver ............................................................................................ 358 Functional Outline of LCD Controller/Driver .................................................................................... 359 LCD Segment Register and LCD Group Register ............................................................................ 361 Output Timing Control Block and Segment/Port Select Block ....................................................... 368 Using LCD Controller/Driver .............................................................................................................. 374 Reset Status ........................................................................................................................................ 376
22. KEY SOURCE CONTROLLER/DECODER .................................................................................. 377
22.1 22.2 22.3 Configuration of Key Source Controller/Decoder ............................................................................ 377 Functional Outline of Key Source Controller/Decoder .................................................................... 378 Key Source Data Setting Block ......................................................................................................... 380
10
PD17010
22.4 22.5 22.6 22.7 Output Timing Control Block and Segment/Port Select Block ....................................................... 382 Key Input Block ................................................................................................................................... 386 Using Key Source Controller/Decoder .............................................................................................. 389 Reset Status ........................................................................................................................................ 397
23. PD17010 INSTRUCTION ............................................................................................................. 398
23.1 23.2 23.3 Instruction Set ..................................................................................................................................... 398 Instruction List .................................................................................................................................... 399 Assembler (AS17K) Embedded Macro Instructions ........................................................................ 401
24. PD17010 RESERVED WORDS ................................................................................................... 402
24.1 Reserved Word List ............................................................................................................................ 402
25. ELECTRICAL SPECIFICATIONS ................................................................................................. 409 26. PACKAGE .................................................................................................................................... 413 27. RECOMMENDED SOLDERING CONDITIONS ............................................................................ 415 APPENDIX A. NOTES ON CONNECTING CRYSTAL RESONATOR ................................................ 416 APPENDIX B. DIFFERENCES AMONG PD17010, PD17003A, AND PD17005 .......................... 417 APPENDIX C. DEVELOPMENT TOOLS ............................................................................................ 420
11
PD17010
1. PIN FUNCTIONS 1.1 Pin Function List
Pin No. 79 80 1 2 3 4 5 6 7 8 9 10 Symbol P0C3 P0C2 P0C1 P0C0 P0A3/SDANote P0A2/SCLNote P0A1/SCK0 P0A0/SO0 P0B3/SI0 P0B2/SCK1 P0B1/SO1 P0B0/SI1 Port 0A, port 0B, or serial interface I/O. N-ch open-drain Withstanding 5 V P0A3/SDA, P0A2/SCL CMOS push-pull P0A1/SCK0, P0A0/SO0, P0B3, P0B2/SCK1, P0B1/SO1, P0B0 Input P0A3-P0A0, P0B3-P0B0 4-bit I/O port. Can be set in input or output mode in 4-bit units. Function Output Format CMOS push-pull Power-ON Reset Input
* P0A3-P0A0
* 4-bit I/O port * Can be set in input or output mode in 1-bit units
* P0B3-P0B0
* 4-bit CMOS I/O port * Can be set in input or output mode in 1-bit units
* SDA, SCL
* SDA : Serial data I/O * SCL : serial clock I/O
* SCK0, SO0, SI0
* SCK0 : Serial clock I/O * SO0 * SI0 : Serial data output : Serial data input
(SDA and SCL cannot be used simultaneously with SCK0, SI0, and SO0.)
* SCK1, SO1, SI1 output
* SCK1 : Serial clock I/O * SO1 * SI1 : Serial data output : Serial data input
SDA, SCL, SCK0, SI0, SCK1, and SI1 are Schmitt trigger input pins with hysteresis. 11 12 INT1 INT0 Edge-detectable vector interrupts. Either rising edge or falling edge can be selected. These pins are Schmitt trigger input pins with hysteresis. Exercise care that voltage higher than VDD is not applied to INTP0 pin on power application. If voltage higher than VDD is applied, PD17010 may not operate correctly. -- Input
Note
The P0A3/SDA and P0A2/SCL are N-ch open-drain output pins and must be connected with external pullup resistors.
12
PD17010
Pin No. 13
Symbol CE
Function Selects operation of PD17010 and inputs reset signal. (1) Device operation selection The PLL frequency synthesizer can operate while CE pin is high. When CE pin is low, the PLL frequency synthesizer is automatically disabled (operation inhibited) internally. (2) Reset signal input When CE pin goes high, device is reset in synchronization with internal basic timer 0 carry FF (CE reset). This pin does not accept high or low level of less than 110 to 165 s to prevent malfunctioning due to noise. Input signal level of this pin can be detected by CEJDG register (address 07H) of register file. At this time, contents of CEJDG register are not changed by low or high level of less than 110 to 165 s. This pin is Schmitt trigger input pin with hysteresis. Exercise care that voltage higher than VDD is not applied to this pin on power application. If voltage higher than VDD is applied,
Output Format --
Power-ON Reset Input
PD17010 may not operate correctly.
14 P1A3 I/O of port 1A and input of external gate counter. CMOS push-pull (P1A3-P1A0) Input (P1A3-P1A0)
* P1A3-P1A0
16 17 P1A1 P1A0/FCG * 4-bit CMOS I/O port * Can be set in input or output mode in 1-bit units
* FCG
* Input to frequency counter for external gate 18 19 20 21 P1B3/PWM2Note P1B2/PWM1Note P1B1/PWM0 P1B0/CGP
Note
Port 1B, and output of D/A converter and clock generator port.
N-ch open-drain Withstanding 16 V P1B3-PWM2
Outputs undefined data (P1B3-P1B0)
* P1B3-P1B0
* 4-bit output port
* PWM2-PWM0
* Output of D/A converter with 8-bit resolution
P1B1-PWM0 CMOS push-pull (P1B0-CGP) CMOS push-pull Outputs undefined data
* CGP
* Clock generator port output 22 P1C3 4-bit CMOS output port
25
P1C0
Note
The P1B3/PWM2 through P1B1/PWM0 are N-ch open-drain output pins and must be connected with external pull-up resistors.
13
PD17010
Pin No. 26 27 28 29
Symbol P1D3/FMIFC P1D2/AMIFC P1D1/ADC1 P1D0/ADC0
Function Port 1D, input to frequency counter, and analog input to A/D converter
Output Format --
Power-ON Reset Input (P1D3-P1D0)
* P1D3-P1D0
* 4-bit input port
* FMIFC, AMIFC
* Frequency measurable with FM and AM intermediate frequency counters Input Pin P1D3/FMIFC Input Frequency Input Amplitude (MHz) (VP-P) 5-15 10.5-10.9 P1D2/AMIFC 0.1-1 0.44-0.46 0.3 0.06 0.3 0.05
These pins are input pins to AC amplifier. Cut off DC components of input signals with capacitor.
* ADC1, ADC0
* Analog inputs to 6-bit resolution A/D converter 30 41 VDD1 VDD2 Positive power supply. Supplies 5 V 10% when CPU and peripheral functions operate. When clock is stopped, data can be retained at 2.2 V. When VDD rises, internal power-ON reset circuit resets -- --
PD17010.
Do not apply voltage higher than VDD pin to any pin other than VDD pins (VDD1 and VDD2 pins). Especially exercise care when raising both VDD and CE pins simultaneously as it may cause latch up. Be sure to connect VDD1 and VDD2 pins to the same voltage level. VDD2 pin supplies power to crystal oscillation circuit (XIN and XOUT pins) and error out circuit (EO0 and EO1 pins), and VDD1 pin supplies power to the other circuits.
14
PD17010
Pin No. 31 32
Symbol VCOL VCOH
Function Inputs local oscillation frequency to PLL. Two types of division modes are selectable: direct division (MF mode) and pulse swallow division (HF and VHF modes). Division Mode Input Input Frequen- Input Voltage Pin cy (MHz) (VP-P) Direct division VCOL (MF) Pulse swallow VCOL (HF) Pulse swallow VCOH (VHF) 0.5-30 5-40 9-150 0.3 0.3 0.3
Output Format --
Power-ON Reset Input
These pins are input pins to AC amplifier. Cut off DC components of input signals with capacitor. 33 34 35 36 37 GND XOUTNote XIN
Note
Ground Connects crystal resonator. Connect 4.5-MHz crystal resonator to these pins. Output from charge pump of PLL frequency synthesizer. If the value resulting from dividing local oscillation (VCO) frequency input to VCOL pin (pin 31) or VCOH pin (pin 32) is higher than reference frequency, EO0 and EO1 pins output high level; if it is lower than reference frequency, EO0 and EO1 pins output low level. If it coincides with reference frequency, EO0 and EO1 pins float. Because the same signal is output to EO0 and EO1 pins, either pin can be used.
-- CMOS push-pull -- CMOS 3-state
-- --
EO0 EO1
High impedance
38
NC
No connection
--
--
40 42 P2A0 1-bit CMOS output port CMOS push-pull Outputs undefined data 43 44 COM1 COM0 Outputs common signal of LCD controller/driver. These pins output low level in display off mode, at power-ON reset, and on execution of clock stop instruction. CMOS ternary output Low-level output
Note
Refer to APPENDIX A. NOTES ON CONNECTING CRYSTAL RESONATOR.
15
PD17010
Pin No. 45
Symbol LCD29/P0F3
Function Output of ports 0F, 0E, 0X, 0Y, segment signal output of LCD controller/driver, and key source
Output Format CMOS push-pull
Power-ON Reset Low-level output (LCD29-LCD0)
48 49
LCD26/P0F0 LCD25/P0E3
signal output of key matrix.
* P0F3-P0F0
* 4-bit CMOS output port
52 53
LCD22/P0E0 LCD21/P0X5
* P0E3-P0E0
* 4-bit CMOS output port
* P0X5-P0X0
58 59 LCD16/P0X0 LCD15/P0Y15/KS15 * 6-bit CMOS output port
* P0Y15-P0Y0
* 16-bit CMOS output port
74
LCD0/P0Y15/KS0
* LCD29-LCD0
* Segment signal output of LCD controller/driver
* KS15-KS0
* Key source signal output of key matrix 75 P0D3/ADC5 Port 0D, analog input to A/D converter, and key source signal return input to LCD segment. 78 P0D0/ADC2 -- Input with pull-down resistor (P0D3-P0D0)
* P0D3-P0D0
* 4-bit input port * Internal pull-down resistor is always on.
* ADC5-ADC2
* Analog input to 6-bit resolution A/D converter * Internal pull-down resistor is off.
* Key source signal return input
* Internal pull-down resistor is on only during key source output (220 s) when LCD segment pin is used as key source, and is off during LCD segment signal output.
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PD17010
1.2 Notes on Using General-Purpose Ports
1.2.1 Data bits of port register To read the input data of and to set output data to ports 0A, 0B, 0C, 0D, 1A, 1B, 1C, 1D, and 2A, the corresponding port register (P0A through P2A registers) in the data memory is used. At this time, the P0A3 pin of port 0A corresponds to the most significant bit of port register P0A, and P0A0 pin corresponds to the least significant bit. The same applies to ports 0B, 0C, 0D, 1A, 1B, 1C, 1D, and 2A. Output data is set to ports 0E, 0F, 0X, and 0Y by the LCD group register via the LCD segment register on the data memory or the data buffer. 1.2.2 I/O ports (ports 0A, 0B, 0C, and 1A) (1) When each port is set in input mode When an instruction that reads the contents of each port register on the data memory (when the address of the port register is specified as m of SKT m, #n or ADD r, m) is executed, the status of each port pin is used as the value of the port register. When an instruction that writes data to a port register (specified by m of MOV m, #n4 or r of ADD r, m) is executed, the value of that data is written to that output data latch circuit. (2) When each port is set in output mode When an instruction that writes data to each port register is executed, the value of that data is written to the output data latch circuit, and is output from each pin. When an instruction that reads the contents of each port register is executed, the contents of the output data latch are used as the value of the port register. However, if an instruction that reads the contents of a port register is executed to the P0A3/SDA and P0A2/SCL pins, the pin status which is different from the output data may be read. All the above port pins are set in the input mode at power-ON reset, CE reset, and on execution of the clock stop instruction. At power-ON reset, the contents of the output data latch circuit are undefined. Unless data is written to the port register before a port is set in the output mode, therefore, undefined data is output. At CE reset and on execution of the clock stop instruction, the contents of the output data latch circuit remain unchanged. 1.2.3 Output ports (ports 1B, 1C, 0F, 0E, 0X, and 0Y) An output port writes the value of a port register to the output data latch circuit and outputs this value from each output pin when an instruction that writes data to the port register is executed. When an instruction that reads the value of the port register is executed, the status of the output data latch circuit is set to the port register. At power-ON reset, undefined data is output. At CE reset and on execution of the clock stop instruction, the previously output data is retained. However, ports 0E, 0F, 0X, and 0Y automatically output a low level at power-ON reset, and also on execution of the clock stop instruction.
17
PD17010
1.3 Equivalent Circuits of Pins
(1) P0A (P0A0/SO0) P0B (P0B1/SO1) P0C (P0C3, P0C2, P0C1, P0C0)Note P1A (P1A3, P1A2, P1A1, P1A0/FCG) (I/O)
VDD
RESET
VDD
Note (2)
The RESET signal is not supplied to P0C. P0A (P0A1/SCK0), P0B (P0B3/SI0, P0B2/SCK1, P0B0/SI1)
VDD
(hysteresis input or output)
RESET
VDD
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PD17010
(3) P0A (P0A3/SDA, P0A2/SCL) (hysteresis input or output)
VDD
(4)
P1B (P1B0/CGP) P1C (P1C3, P1C2, P1C1, P1C0) P2A (P2A0) LCD0/P0Y0/KS0-LCD29/P0F3 (output)
VDD
(5)
P1B (P1B3/PWM2, P1B2/PWM1, P1B1/PWM0) (output)
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(6) P0D (P0D3/ADC5, P0D2/ADC4, P0D1/ADC3, P0D0/ADC2) (input)
VDD A/D converter
High ON resistor
(7)
P1D (P1D1/ADC1, P1D0/ADC0) (input)
VDD A/D converter
(8)
P1D (P1D3/FMIFC, P1D2/AMIFC) (input)
VDD
General-purpose port
VDD
High ON resistor VDD
Frequency counter
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(9) CE INT1 INT0
VDD
(Schmitt trigger input)
(10) XOUT (output), XIN (input)
VDD
High ON resistor VDD
XIN
Internal clock
High ON resistor XOUT
(11) EO1 EO0 (output)
VDD
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PD17010
(12) COM1 COM0
(output)
VDD
VDD
High ON resistor
High ON resistor
(13) VCOH VCOL
(input)
VDD
High ON resistor
VDD
High ON resistor
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PD17010
1.4 Processing of Unused Pins
It is recommended that the unused pins be processed as shown below. Table 1-1. Processing of Unused Pins
Pin Name Port pins P0D0/ADC2-P0D3/ADC5 P1D0/ADC0Note 2 P1D1/ADC1Note 2 P1D2/AMIFCNotes 2, 3 P1D3/FMIFCNotes 2, 3 P0E0/LCD22-P0E3/LCD25 P0F0/LCD26-P0F3/LCD29 P0X0/LCD16-P0X5/LCD21 P0Y0/LCD0/KS0P0Y15/LCD15/KS15 P1B0/CGP P1C0-P1C3 P2A0 P1B1/PWM0-P1B3/PWM2 P0A0/SO0 P0A1/SCK0 P0A2/SCL P0A3/SDA P0B0/SI1 P0B1/SO1 P0B2/SCK1 P0B3/SI0 P0C1/P0C3 P1A0/FCGNote 2 P1A1/P1A3Note 2 Pins other than port pins CE INT0, INT1 VCOH, VCOL COM0, COM1 EO0, EO1 Output Input Connect to VDD via resistorNote1 Connect each pin to GND via resistorNote1 Set disable via software, and open Open N-ch open-drain output I/O
Note 4
I/O Input
Recommended Processing Individually connect to GND via resistorNote 1 Individually connect to VDD or GND via resistorNote 1
Set as P1D2 and connect to VDD or GND via resistorNote 1 Set as P1D3 and connect to VDD or GND via resistor CMOS push-pull output Open
Note 1
Set to low level output via software, and open Set as general-purpose input port via software, and connect each pin to VDD or GND via resistorNote 1
Notes 1. If a pin is externally pulled up (connecting to VDD via resistor) or down (connecting to GND via resistor) with a high resistance, the pin almost goes into a high impedance state. This increases the (inrush) current dissipation of the port. The value of the pull-up or pull-down resistor is generally several 10 kilohms, though this varies and depends on the application circuit. 2. The current dissipation of the general-purpose input port does not increase even in the high-impedance state. 3. Do not set these pins as AMIFC and FMIFC; otherwise, the current dissipation increases. 4. The I/O ports serve as general-purpose input ports at power application, clock stop, and CE reset.
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PD17010
1.5 Notes on Using CE, INT0, and INT1 Pins
The CE, INT0, and INT1 pins have a function to set a test mode (for IC test) in which the internal operations of the
PD17010 are tested, in addition to the functions indicated in 1.1 Pin Function List.
If a voltage higher than VDD is applied to any of these pins, the test mode is set. If a noise higher than VDD is added on any of these pins in the normal operation mode, therefore, the test mode is set by mistake. This may happen if the wiring length of the CE, INT0, and INT1 pins is too long and as a result, noise is added to the circuitry. Therefore, keep the wiring of these pins as short as possible to suppress the noise. If necessary, use an external component as shown below to suppress the noise. * Connect diode with low VF between VDD * Connect capacitor between VDD
VDD
VDD
Diode with low VF CE, INT0, INT1
VDD
VDD
CE, INT0, INT1
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PD17010
2. PROGRAM MEMORY (ROM) 2.1 Outline of Program Memory
Figure 2-1 outlines the program memory. As shown in this figure, the program memory consists of a program memory and a program counter. The addresses of the program memory are specified by the program counter. The program memory has the following two major functions: (1) Stores executed instructions (2) Stores constant data Figure 2-1. Outline of Program Memory
Program counter Specifies address
Program memory . . . Instruction . . . . . . Constant data . . .
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PD17010
2.2 Program Memory
Figure 2-2 shows the configuration of the program memory. As shown, the program memory consists of 7932 steps by 16 bits. Therefore, the program memory address ranges from 0000H to 1EFBH. Because all "instructions" are 16-bit long "1-word instructions", one instruction can be stored in one program memory address. Constant data reads the contents of the program memory to the data buffer by using a table reference instruction. Figure 2-2. Program Memory Configuration
0000H 16 bits
07FFH 0800H
Page 0
2K 8K 0FFFH 1000H Page 1
17FFH 1800H
Page 2
1EFBH 1FFFH
Page 3 Undefined
2.3 Program Counter
Figure 2-3 shows the configuration of the program counter. As shown, the program counter is a 13-bit binary counter. The highest 2 bits, bits b11 and b12, indicate a page. The program counter specifies an address of the program memory. Figure 2-3. Program Counter Configuration
PC12
PC11
PC10
PC9
PC8
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
Page PC
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PD17010
2.4 Program Flow
The program flow is controlled by the program counter that specifies an address of the program memory. The operation to be performed when each instruction is executed is described below. Figure 2-4 shows the value set to the program counter when each instruction is executed. Table 2-1 shows the vector address to be used when an interrupt is accepted. 2.4.1 Branch instruction (1) Direct branch ("BR addr") The branch destination address of the direct branch instruction ranges from 0000H through 1EFBH, i.e., any address of the program memory. (2) Indirect branch ("BR @AR") The branch destination address of the indirect branch instruction ranges from 0000H through 1EFBH, i.e., any address of the program memory. For more information, refer to 5.3 Address Register (AR). 2.4.2 Subroutine (1) Direct subroutine call ("CALL addr") The first address of a subroutine that can be called by the direct subroutine call instruction is within page 0 (address 0000H to 07FFH) of the program memory. (2) Indirect subroutine call ("CALL @AR") The first address of a subroutine that can be called by the indirect subroutine call instruction ranges from 0000H to 1EFBH, i.e., any address of the program memory. For more information, refer to 5.3 Address Register (AR). 2.4.3 Table reference The address that can be referenced by the table reference instruction ("MOVT DBF, @AR") ranges from 0000H to 1EFBH, i.e., any address of the program memory. For more information, refer to 5.3 Address Register (AR) and 9.2.2 Table reference instruction ("MOVT DBF, @AR").
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PD17010
Figure 2-4. Specification by Program Counter for Each Instruction
Program Counter Instruction Page 0 Page 1 BR addr Page 2 Page 3 CALL addr BR CALL @AR @AR 1 1 0 0 1 0 b12 0 0 b11 0 1 b10
Contents of Program Counter (PC) b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
Instruction operand (addr)
Instruction operand (addr)
Contents of address register
MOVT DBF, @AR RET RETSK RETI (return address) Contents of address stack register (ASR) specified by stack pointer (SP)
When interrupt is accepted
Vector address of each interrupt
At power-ON or CE reset
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 2-1. Interrupt Vector Address Order Internal/External 1 2 3 4 5 6 External INT0 pin Interrupt Source Vector Address 0006H 0005H 0004H 0003H 0002H 0001H
Internal/external INT1 pin or timer/counter overflow Internal Internal Internal Internal 12-bit timer Basic timer 1 Serial interface 0 Frequency counter
2.5 Notes on Using Program Memory
The address that can be specified by the program counter ranges from 0000H to 1FFFH. By contrast, the program memory exist at addresses 0000H through 1EFBH. Therefore, do not use an instruction that sets the value of the program counter to 1EFCH to 1FFFH. The addresses 1EFCH through 1FFFH of the program memory are "undefined" values.
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PD17010
3. ADDRESS STACK (ASK) 3.1 Outline of Address Stack
Figure 3-1 outlines the address stack. The address stack consists of a stack pointer and address stack registers. The addresses of the address stack registers are specified by the stack pointer. The address stack saves a return address when a subroutine call instruction is executed or when an interrupt is accepted. The address stack is also used when the table reference instruction is executed. Figure 3-1. Outline of Address Stack
Stack pointer Specifies address
Address stack registers
Return address
3.2 Address Stack Register (ASR)
Figure 3-2 shows the configuration of the address stack registers. Sixteen 16-bit address stack registers, ASR0 through ASR15, are available. However, registers are not allocated to ASR9 through ASR15. Actually, therefore, nine 16-bit registers (ASR0 through ASR8) can be used. The higher 3 bits of ASR0 through ASR8 are fixed to "0". The address stack stores a return address when a subroutine call instruction or table reference instruction is executed, or when an interrupt is accepted.
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PD17010
Figure 3-2. Address Stack Registers Configuration
Stack Pointer (SP) Bit Address b3 b2 b1 b0 0H b12 b11 b10
Address Stack Registers (ASRs) Bit b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
SP3 SP2 SP1 SP0
ASR0
1H
ASR1
2H
ASR2
3H
ASR3
4H
ASR4
5H
ASR5
6H
ASR6
7H
ASR7
8H
ASR8
9H
ASR9 (undefined)
0AH
ASR10 (undefined)
0BH
ASR11 (undefined) Cannot be used
0CH
ASR12 (undefined)
0DH
ASR13 (undefined)
0EH
ASR14 (undefined)
0FH
ASR15 (undefined)
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PD17010
3.3 Stack Pointer (SP)
3.3.1 Configuration and function of stack pointer Figure 3-3 shows the configuration and function of the stack pointer. The stack pointer is a 4-bit binary counter. It specifies the addresses of the address stack registers. The value of the stack pointer can be directly read or written by using a register manipulation instruction. Figure 3-3. Configuration and Function of Stack Pointer
Flag Symbol Name b3 Stack pointer S P (SP) 3 b2 S P 2 b1 S P 1 b0 S P 0 01H Address
Read/ Write
R/W
Specifies addresses of address stack registers (ASRs) 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Address 0 (ASR0) Address 1 (ASR1) Address 2 (ASR2) Address 3 (ASR3) Address 4 (ASR4) Address 5 (ASR5) Address 6 (ASR6) Address 7 (ASR7) Address 8 (ASR8) Address 9 (ASR9) Address 10 (ASR10) Address 11 (ASR11) Address 12 (ASR12) Address 13 (ASR13) Address 14 (ASR14) Address 15 (ASR15)
On reset
Power-ON Clock stop CE
1 1 1
0 0 0
0 0 0
1 1 1
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PD17010
3.4 Operation of Address Stack
3.4.1 Subroutine call instructions ("CALL addr", "CALL @AR") and return instructions ("RET", "RETSK") When a subroutine call instruction is executed, the value of the stack pointer is decremented by one, and a return address is stored to the address stack register specified by the stack pointer. When a return instruction is executed, the contents of the address stack register (return address) specified by the stack pointer are restored to the program counter, and the value of the stack pointer is incremented by one. 3.4.2 Table reference instructions ("MOVT DBF, @AR") When a table reference instruction is executed, the value of the stack pointer is decremented by one, and a return address is stored to the address stack register specified by the stack pointer. Next, the contents of the program memory specified by the address register are read to the data buffer, the contents of the address stack register (return address) specified by the stack pointer are restored to the program counter, and the value of the stack pointer is incremented by one. 3.4.3 When interrupt is accepted or when return instruction ("RETI") is executed When an interrupt is accepted, the value of the stack pointer is decremented by one, and a return address is stored to the address stack register specified by the stack pointer. When the return instruction is executed, the contents of the address stack register (return address) specified by the stack pointer is restored to the program counter, and the value of the stack pointer is incremented by one. 3.4.4 Address stack manipulation instructions ("PUSH AR", "POP AR") When the "PUSH" instruction is executed, the value of the stack pointer is decremented by one, and the contents of the address register are transferred to the address stack register specified by the stack pointer. When the "POP" instruction is executed, the contents of the address stack register specified by the stack pointer are transferred to the address register, and the value of the stack pointer is incremented by one.
3.5 Notes on Using Address Stack
3.5.1 Nesting level The values of the address stack registers (ASR9 through ASR15) are "undefined" when the value of the stack pointer is 09H through 0FH. If a subroutine call instruction or interrupt that exceeds level 9 is used without manipulating the stack, execution returns to an "undefined" address.
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PD17010
4. DATA MEMORY (RAM) 4.1 Outline of Data Memory
Figure 4-1 outlines the data memory. As shown in this figure, the data memory consists of a general-purpose data memory, system register, data buffer, LCD segment register, and port register. The data memory stores data, transfers data with peripheral hardware, sets display data, transfers data with ports, and controls the CPU. Figure 4-1. Outline of Data Memory
Peripheral hardware Transfers data Column address 0 0 1
Row address
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
Data buffer
2 3 4 5 6 7 Port register Port register Port register Port register System register Transfers data Port LCD Transfers data BANK0 LCD segment register BANK1 BANK2 BANK3
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PD17010
4.2 Configuration and Function of Data Memory
Figure 4-2 shows the configuration of the data memory. As shown in this figure, the data memory is divided into four banks with each bank consisting of a total of 128 nibbles (row address 7H and column address 0FH). The data memory is divided by function into the six blocks as described in 4.2.1 through 4.2.6 below. The contents of the data memory can be manipulated by using data memory manipulation instructions, and 4-bit data can be operated, compared, judged, and transferred with a single instruction. Table 4-1 shows the data memory manipulation instructions. 4.2.1 System register (SYSREG) The system register is allocated to addresses 74H through 7FH. Because the system register is allocated regardless of banks, the same system register exist at addresses 74H through 7FH of any bank. For details, refer to 5. SYSTEM REGISTER (SYSREG). 4.2.2 Data buffer (DBF) The data buffer is allocated to addresses 0CH through 0FH of BANK0. For details, refer to 9. DATA BUFFER (DBF). 4.2.3 LCD segment data register (LCD segment register) The LCD segment register is allocated to addresses 60H through 6FH of BANK0 of the data memory. For details, refer to 21. LCD CONTROLLER/DRIVER. 4.2.4 Port data register (port register) The port register is allocated to addresses 70H through 73H of each bank. For details, refer to 15. GENERAL-PURPOSE PORTS. 4.2.5 General-purpose data memory The general-purpose data memory is allocated to an area of the data memory excluding the system register, LCD segment register, and port register. This consists of a total of 432 nibbles (432 x 4 bits) of 96 nibbles of BANK0 and 112 words each of BANK1 through BANK3. 4.2.6 Not provided data memory As a part of the LCD segment register and port register, a data memory area to which nothing is actually allocated exists. For this data memory area, refer to 4.4.2 Notes on not provided data memory, 15. GENERAL-PURPOSE PORTS, and 21. LCD CONTROLLER/DRIVER.
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PD17010
Figure 4-2. Data Memory Configuration
Column address 0123456789ABCDEF 0 1 2 3 4 5 6 7
Row address
Data memory
BANK0 BANK1 BANK2 BANK3
System register
0 0 1
1
2
3
4
5
Column address 6789A
B
C
D
E
F
Data buffer (DBF)
Row address
2 3 4 5 6 7 Port register 0 0 1 1 2 3 4 5 6 BANK0 LCD segment register System register (SYSREG) 7 8 9 A B C D E F General register
Example
Address 1AH of BANK0
b3 b2 b1 b0
Row address
2 3 4 5 6 7 Port register 0 0 1 1 2 3 4 5 6 System register (SYSREG) 7 8 9 A B C D E F BANK1
Row address
2 3 4 5 6 7 Port register 0 0 1 1 2 3 4 5 6 System register (SYSREG) 7 8 9 A B C D E F BANK2
Row address
2 3 4 5 6 7 System register (SYSREG) Same system register exists BANK3
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PD17010
Table 4-1. Data Memory Manipulation Instruction List Function Operation Addition Instruction ADD ADDC Subtraction SUB SUBC Logical AND OR XOR Comparison SKE SKGE SKLT SKNE Transfer MOV LD ST Judgment SKT SKF
4.3 Addressing of Data Memory
Figure 4-3 shows addressing of the data memory. A data memory address is specified by bank, row and column addresses. The row and column addresses are directly specified by using a data memory manipulation instruction, but the bank is specified by the contents of the bank register. For the details of the bank register, refer to 5. SYSTEM REGISTER (SYSREG). Figure 4-3. Addressing of Data Memory
Bank b3 b2 b1 b0
Row Address b2 b1 b0 b3
Column Address b2 b1 b0
Data memory address
M
Bank register
Instruction operand
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PD17010
4.4 Notes on Using Data Memory
4.4.1 On power-ON reset At power-ON reset, the contents of the general-purpose data memory are "undefined". Initialize the general-purpose data memory as necessary. 4.4.2 Notes on not provided data memory If a data memory manipulation instruction is executed to manipulate the address of a data memory area to which nothing has been allocated, the following operations are performed: (1) Device operation When a read instruction is executed, "0" is read. Nothing is changed if a write instruction is executed. (2) Assembler (AS17K) operation Assembly is executed normally. An error does not occur. (3) Emulator (IE-17K) operation When a read instruction is executed, "0" is read. Nothing is changed if a write instruction is executed. An error does not occur.
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PD17010
5. SYSTEM REGISTER (SYSREG) 5.1 Outline of System Register
Figure 5-1 shows the location of the system register on the data memory and its outline. As shown in this figure, the system register is located at addresses 74H through 7FH of the data memory independently of the bank. Therefore, the same system register exists at addresses 74H through 7FH of any bank. Because the system register is located on the data memory, it can be manipulated by any data memory manipulation instruction. The system register consists of seven types of registers by function. Figure 5-1. Location on Data Memory and Outline of System Register
Column address 0 0 1 2 3 4 5 6 7 1 2 3 4 5 6 7 8 9 A B C D E F
Data memory
Row address
BANK0 BANK1 BANK2 BANK3 System register
Address
74H
75H
76H
77H
78H
79H
Name
Address register (AR)
Window register (WR)
Bank register (BANK)
Outline
Controls program memory address
Transfers data with register file
Specifies bank of data memory
Address
7AH
7BH Index register (IX)
7CH
7DH
7EH
7FH
Name Data memory row address pointer (MP)
General register pointer (RP)
Program status word (PSWORD)
Outline
Modifies address of data memory
Specifies address of general register
Controls operation
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PD17010
5.2 System Register List
Figure 5-2 shows the configuration of the system register. Figure 5-2. System Register Configuration
Address
74H
75H
76H System register
77H
78H
79H
Name
Address register (AR)
Window register (WR)
Bank register (BANK)
Symbol Bit b3
AR3 b2 b1 b0 b3
AR2 b2 b1 b0 b3
AR1 b2 b1 b0 b3
AR0 b2 b1 b0 b3
WR b2 b1 b0 b3
BANK b2 b1 b0
Data
0
0
0
0
0
Address
7AH
7BH
7CH
7DH
7EH
7FH
System register Index register (lX) Data memory row address pointer (MP) IXH Symbol MPH Bit b3 b2 b1 b0 b3 MPL b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 IXM IXL RPH RPL PSW
General register pointer (RP)
Name
Program status word (PSWORD)
M Data P E (MP) 0 0 (IX) 0 0 (RP) B C D C M P C Y Z I X E
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PD17010
5.3 Address Register (AR)
5.3.1 Configuration of address register Figure 5-3 shows the configuration of the address register. As shown in this figure, the address register consists of 16 bits, 74H through 77H (AR3 through AR0), of the system register. Actually, however, it operates as a 13-bit register because the highest 3 bits are always fixed to "0". Figure 5-3. Address Register Configuration
Address Name Symbol Bit b3 AR3 b2 b1 b0
>
74H
75H
76H
77H
Address Register (AR) AR2 b3 b2 b1 b0 b3 AR1 b2 b1 b0 b3 AR0 b2 b1 b0
>
M Data S 0 0 0 B
<
L S B
<
On reset
Power-ON Clock stop CE
0 0 0
0 0 0
0 0 0
0 0 0
Remark Power-ON : on power-ON reset Clock stop : on execution of clock stop instruction CE : on CE reset
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PD17010
5.3.2 Function of address register The address register specifies a program memory address when the table reference instruction ("MOVT DBF, @AR"), stack manipulation instruction ("PUSH AR", "POP AR"), indirect branch instruction ("BR @AR"), or indirect subroutine call instruction "CALL @AR") is executed. A dedicated instruction ("INC AR") that can increment the contents of the address register by one at a time is provided. The following paragraphs (1) through (5) describe the operation of the address register when each instruction is executed. (1) Table reference instruction ("MOVT DBF, @AR") This instruction reads the constant data (16 bits) of the program memory address specified by the contents of the address register to the data buffer. The constant data storing address that can be specified by the address register is 0000H to 1EFBH. (2) Stack manipulation instruction ("PUSH AR", "POP AR") When the "PUSH AR" instruction is executed, the contents of the stack pointer are decremented by one, and the contents of the address register (AR) are stored to the address stack register specified by the stack pointer. When the "POP AR" instruction is executed, the contents of the address stack register specified by the stack pointer are transferred to the address register, and the contents of the stack pointer are incremented by one. (3) Indirect branch instruction ("BR @AR") This instruction branches execution to the program memory address specified by the contents of the address register. The branch address that can be specified by the address register is 0000H to 1EFBH. (4) Indirect subroutine call instruction ("CALL @AR") This instruction calls the subroutine at the program memory address specified by the contents of the address register. The first address of the subroutine that is specified by the address register is 0000H to 1EFBH. (5) Address register increment instruction ("INC AR") This instruction increments the contents of the address register by one. Because the address register consists of 13 bits, if "INC AR" instruction is executed when the contents of the address register are "1FFFH", the address register contents are cleared to "0000H". 5.3.3 Address register and data buffer The address register can transfer data via data buffer as a part of the peripheral hardware. For details, refer to 9. DATA BUFFER (DBF). 5.3.4 Notes on using address register Because the address register consists of 13 bits, its contents can be up to 1FFFH theoretically. However, the highest address of the program memory is 1EFBH. Therefore, the maximum value that can be set to the address register is 1EFBH.
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5.4 Window Register (WR)
5.4.1 Configuration of window register Figure 5-4 shows the configuration of the window register. As shown in this figure, the window register consists of 4 bits of address 78H of the system register. Figure 5-4. Window Register Configuration
Address Name Symbol Bit b3
>
78H Window Register (WR) WR b2 b1 b0
>
M S Data B
<
L S B
<
On reset
Power-ON Clock stop CE
Undefined Retains previous status
5.4.2 Function of window register The window register transfers data with the register file (RF) described later. To transfer data between the window register and register file, dedicated instructions "PEEK WR, rf" and "POKE rf, WR" are used (where rf is the address of the register file). The following paragraphs (1) and (2) describe the operation to be performed when each instruction is executed. For more information, refer to 8. REGISTER FILE (RF). (1) "PEEK WR, rf" instruction This instruction transfers the contents of the register file addressed by "rf" to the window register. (2) "POKE rf, WR" instruction This instruction transfers the contents of the window register to the register file addressed by "rf".
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5.5 Bank Register (BANK)
5.5.1 Configuration of bank register Figure 5-5 shows the configuration of the bank register. As shown in this figure, the bank register consists of 4 bits of address 79H (BANK) of the system register. Actually, however, the bank register operates as a 2-bit register because its highest 2 bits are always fixed to "0". Figure 5-5. Bank Register Configuration
Address Name Symbol Bit b3
79H Bank Register (BANK) BANK b2 b1
>
b0
>
M Data 0 0 S B
< On reset
L S B
<
Power-ON Clock stop CE
0 0 0
5.5.2 Function of bank register The bank register specifies a bank of the data memory. Table 5-1 shows the relation between the value of the bank register and the bank of the data memory. Because the bank register exists on the system register, its contents can be rewritten regardless of the bank currently specified. Therefore, the bank register can be manipulated independently of the current bank status. Table 5-1. Specifying Bank of Data Memory Bank Register (BANK) b3 0 0 0 0 b2 0 0 0 0 b1 0 0 1 1 b0 0 1 0 1 BANK0 BANK1 BANK2 BANK3 Bank of Data Memory
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5.6 Index Register (IX) and Data Memory Row Address Pointer (MP: Memory Pointer)
5.6.1 Configuration of index register and data memory row address pointer Figure 5-6 shows the configuration of the index register and data memory row address pointer. As shown in this figure, the index register consists of an index register (IX) made up of a total of 11 bits (the lower 3 bits (IXH) of the address 7AH, and addresses 7BH and 7CH (IXM and IXL) of the system register) and an index enable flag (IXE) that is the least significant bit of address 7FH (PSW). The data memory row address pointer (memory pointer) consists of a data memory row address pointer made up of a total of 7 bits (the lower 3 bits of 7AH (MPH) and 7BH (MPL)) and a data memory row address pointer enable flag (memory pointer enable flag: MPE) that is the most significant bit of 7AH (MPH). This means that the higher 7 bits of the index register are shared by the data memory row address pointer. However, the highest 2 bits of the index register and data memory row address pointer (bits b2 and b1 of 7AH) are always fixed to "0". Figure 5-6. Configuration of Index Register and Data Memory Row Address Pointer
Address Name Memory Pointer (MP) IXH Symbol MPH Bit b3 b2 b1 b0 b3 MPL b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 IXM IXL PSW 7AH 7BH Index Register (IX) 7CH 7EH 7FH Program Status Word (PSWORD)
>
M P E Data 0 0
>
M S B
<
L S B IX
<
I X E
>
M S B
<
MP
On reset
Power-ON Clock stop CE
0 0 0
0 0 0
<
>
L S B
0 0 0
0 0 0
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5.6.2 Function of index register and data memory row address pointer The index register and data memory row address pointer modify the addresses of the data memory. The following paragraphs (1) and (2) describe the functions of the index register and data memory row address pointer. A dedicated instruction ("INC IX") that can increment the contents of the index register by one at a time is provided. For the details of address modification, refer to 7. ALU (ARITHMETIC LOGIC UNIT) BLOCK. (1) Index register A data memory address is modified according to the contents of the index register when a data memory manipulation instruction is executed. However, this modification is valid only when the IXE flag is set to "1". The address is modified by ORing the bank, row address, and column address of the data memory with the contents of the index register, and an instruction is executed to the data memory specified by the result of the OR operation (called actual address). Address modification by the index register is subjected to all data memory manipulation instructions. The following instructions are not subject to modification. INC INC MOVT PUSH POP PEEK POKE GET PUT BR BR AR IX DBF, @AR AR AR WR, rf rf, WR DBF, p p, DBF addr @AR RORC CALL CALL RET RETSK RETI EI DI STOP HALT NOP s h r addr @AR
(2) Data memory row address pointer When a general register indirect transfer instruction ("MOV @r, m", "MOV m, @r") is executed, the address of the indirect transfer destination is modified. This modification, however, is valid only when the MPE flag is set to "1". To modify the address, the bank and row address at the indirect transfer destination are replaced with the contents of the data memory row address pointer. Instructions other than the general register indirect transfer instruction is not subject to address modification. (3) Index register increment instruction ("INC IX") This instruction increments the contents of the index register by one at a time. Because the index register consists of 9 bits, if the "INC IX" instruction is executed when the contents of the index register are "1FFH", the index register is cleared to "000H".
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5.7 General Register Pointer (RP)
5.7.1 Configuration of general register pointer Figure 5-7 shows the configuration of the general register pointer. As shown in this figure, the general register pointer consists of a total of 7 bits: 4 bits of the address 7DH (RPH) of the system register and the higher 3 bits of address 7EH (RPL). Actually, however, only the lower 5 bits (the lower 2 bits of address 7DH and the higher 3 bits of address 7EH) are valid because the higher 2 bits of address 7DH are always fixed to 0. Figure 5-7. General Register Pointer Configuration
Address Name Symbol Bit b3 7DH General Register Pointer (RP) RPH b2 b1
>
7EH
RPL b0 b3 b2 b1
>
b0
M Data 0 0 S B
<
L S B
<
B C D
On reset
Power-ON Clock stop CE
0 0 0
0 0 0
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5.7.2 Function of general register pointer The general register pointer specifies a general register on the data memory. Figure 5-8 shows the addresses of the general register specified by the general register pointer. As shown in this figure, the higher 4 bits of the general register pointer (RPH: address 7DH) specify a bank, and the lower 3 bits (RPL: address 7EH) specify a row address. Because the number of valid bits of the general register pointer is 5, the row addresses (0H through 7H) of all the banks (BANK0 through BANK3) can be specified as a general register. For the details of the operation of the general register, refer to 6. GENERAL REGISTER (GR). Figure 5-8. Address of General Register Specified by General Register Pointer
General Register Pointer (RP) RPH b3 b2 b1
>
RPL b0 b3 b2 b1
>
b0 B C D
0
0
M S B
<
L S B
<
Specifies row address of each bank Specifies bank Bank 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 BANK0 Row address 0H 1H 2H 3H
1 1 1 1
1 1 1 1
1 1 1 1
0 0 1 1
0 1 0 1 BANK3
4H 5H 6H 7H
5.7.3 Notes on using general register pointer The least significant bit of address 7EH (RPL) of the general register pointer is allocated as the BCD flag of the program status word. When rewriting RPL, therefore, pay attention to the value of the BCD flag.
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5.8 Program Status Word (PSWORD)
5.8.1 Configuration of program status word Figure 5-9 shows the configuration of the program status word. As shown in this figure, the program status word consists of a total of 5 bits: the least significant bit of address 7EH (RPL) of the system register and 4 bits of address 7FH (PSW). Each bit of the program status word has its own function, and the program status word consists of BCD flag (BCD), compare flag (CMP), carry flag (CY), zero flag (Z), and index enable flag (IXE). Figure 5-9. Program Status Word Configuration
Address Name Symbol Bit b3 7EH 7EH Program Status Word (PSWORD) PSW b0 B C Data D b3 C M P b2 C Y b1 Z b0 I X E
(RP) RPL b2 b1
On reset
Power-ON Clock stop CE
0 0 0
0 0 0
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5.8.2 Function of program status word The program status word is a register that sets the condition for the operation of the ALU (Arithmetic Logic Unit) or transfer instruction or indicates the result of an operation. Table 5-2 outlines the function of each flag of the program status word. For details of the operation, refer to 7. ALU (ARITHMETIC LOGIC UNIT) BLOCK. Table 5-2. Functional Outline on Each Flag of Program Status Word
Program Status Word (PSWORD) PSW b0 B C D b3 C M P b2 C Y b1 Z b0 I X E Flag Name Function Modifies address of data memory when data memory manipulation instruction is executed 0: Does not modify 1: Modifies
(RP) RPL b3 b2 b1
Index enable flag (IXE)
Zero flag (Z)
Indicates that resultof arithmeticoperation is zero. Note that status of 0 and 1 of this flag differs depending on contents of compare flag.
Carry flag (CY)
Indicates occurrence of carry or borrow as result of executing addition or subtraction instruction. Reset to 0 if carry or borrow does not occur. Set to 1 if carry or borrow occurs. This flag is also used as shift bit of "RORC r" instruction.
Compare flag (CMP)
This flag specifies whether or not resultof arithmetic operation isstored to data memory or general regizster. 0: Stores result 1: Does not store result This flag specifies whether arithmetic operation is performed in binary or decimal 1: Binary operation 0: Decimal operation
BCD flag (BCD)
5.8.3 Notes on using program status word If an arithmetic operation (addition or subtraction) instruction is executed to the program status word, the result of the arithmetic operation is stored to the program status word. For example, when an operation that generates a carry is executed and if the result of the operation is 0000B, 0000B is stored to PSW.
5.9 Notes on Using System Register
Data of the system register that is fixed to "0" is not affected in any way even if a write instruction is executed to it. If this data is read, "0" is always read.
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6. GENERAL REGISTER (GR) 6.1 Outline of General Register
Figure 6-1 outlines the general register. As shown in this figure, the general register consists of a general register pointer and a general register. The bank and row address of the general register are specified by the general register pointer. The general register is used to transfer data or execute operations between data memory areas. Figure 6-1. Outline of General Register
Column address Data memory
Row address
General register pointer
General regjster Transfer, operation
BANK0 BANK1 BANK2 BANK3 System register
6.2 General Register
The general register consists of 16 nibbles (16 x 4 bits) which are at the same row addresses on the data memory. For the ranges of banks and row addresses that can be specified for the general register pointer and general register, refer to 5.7 General Register Pointer (RP). The 16 nibbles at the same row addresses specified as the general register can execute operations and transfer data with a data memory area with a single instruction. This means that operation and data transfer between data memory areas can be executed with a single instruction. The general register can be controlled by using data memory manipulation instructions in the same manner as the other data memory areas.
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6.3 General Register Address Generation by Each Instruction
6.3.1 and 6.3.2 describe how the addresses of the general register are generated by each instruction. For the details of the operation of each instruction, refer to 7. ALU (ARITHMETIC LOGIC UNIT) BLOCK. 6.3.1 Addition ("ADD r, m", "ADDC r, m"), Subtraction ("SUB r, m", "SUBC r, m"), Logical operation ("AND r, m", "OR r, m", "XOR r, m"), Direct transfer ("LD r, m", "ST m, r"), Rotation processing ("RORC r") instruction Table 6-1 shows the address of general register "R" specified by the operand "r" of an instruction. Instruction operand "r" only specifies a column address. Table 6-1. General Register Address Generation
Bank b3 b2 b1 b0
Row Address Column Address b2 b1 b0 b3 b2 b1 b0
General register address
R
Contents of general register pointer
r
6.3.2 Indirect transfer ("MOV @r, m", "MOV m, @r") instructions Table 6-2 shows the address of the general register "R" specified by instruction operand "r" and indirect transfer address specified by "@R". Table 6-2. General Register Address Generation
Bank b3 b2 b1 b0
Row Address Column Address b2 b1 b0 b3 b2 b1 b0
General register address
R
Contents of general register pointer
r
Indirect transfer address
@R
Same as data memory
Contents of R
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6.4 Notes on Using General Register
6.4.1 Row address of general register Because the row address of the general register is specified by the general register pointer, the currently specified bank may be different from the bank of the general register. 6.4.2 Operation between general register and immediate data There is no instruction povided to execute an operation between the general register and immediate data. To execute an operation instruction between the general register and immediate data, the general register must be treated as a data memory area.
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7. ALU (ARITHMETIC LOGIC UNIT) BLOCK 7.1 Outline of ALU Block
Figure 7-1 outlines the ALU block. As shown in this figure, the ALU block consists of an ALU, temporary registers A and B, program status word, decimal adjustment circuit, and data memory address control circuit. The ALU executes operation, judgment, comparison, rotation, and transfer of 4-bit data on the data memory. Figure 7-1. Outline of ALU Block
Data bus
Address control
Temporary register A
Temporary register B
Program status word Carry/borrow/zero detection/decimal/ storage specification ALU * Arithmetic operation * Logical operation * Bit judgment * Comparison * Rotation processing * Transfer
Index modification memory pointer
Data memory
Decimal adjustment
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7.2 Configuration and Function of Each Block
7.2.1 ALU The ALU executes arithmetic operation, logical operation, bit judgment, comparison, rotation processing, and transfer of 4-bit data by using an instruction specified by the program. 7.2.2 Temporary registers A and B Temporary registers A and B temporarily store 4-bit data. These registers are automatically used when an instruction is executed, and cannot be controlled by program. 7.2.3 Program status word The program status word controls the operation and stores the status of the ALU. For the details of the program status word, refer to 5.8 Program Status Word (PSWORD). 7.2.4 Decimal adjustment circuit The decimal adjustment circuit converts the result of an arithmetic operation into a decimal number if the BCD flag of the program status word is set to "1" when the arithmetic operation is executed. 7.2.5 Address control circuit The address control circuit specifies an address of the data memory. At this time, it also controls address modification by the index register and data memory row address pointer.
7.3 ALU Processing Instruction List
Table 7-1 lists the operations of the ALU when each instruction is executed. Table 7-2 shows modification of data memory addresses by the index register and data memory row address pointer. Table 7-3 shows the decimal adjustment data when a decimal operation is performed.
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Table 7-1. ALU Processing Instruction Operation List
ALU Function Instruction Value of BCD Flag Addition ADD r, m m, #n4 ADDC r, m m, #n4 Subtraction SUBC SUB r, m m, #n4 r, m m, #n4 Logical operation AND OR r, m m, #n4 r, m m, #n4 XOR r, m m, #n4 Judgment SKT SKF m, #n m, #n Any (retained) Any (retained) 1 1 0 0 Difference in Operation Depending on Program Status Word (PSWORD) Address Modification Index Memory Pointer Set if result of operation is 0000B; otherwise, reset Retains status if result of operation is 0000B; otherwise, reset Set if result of operations is 0000B; otherwise, reset Retains status if result of operation is 0000B; otherwise, reset Retains previous status Retains previous status Modified Not modified Modified Not modified
----------------------------------------------------------------------------------------------------------------------------------------------------------------------
Value of CMP Flag 0
Operation
Operation of CY Flag
Operation of Z Flag
Stores result of binary operation
Set if carry or borrow
1
Does not store result occurs; of binary operation otherwise, reset
0
Stores result of decimal operation
1
Does not store result of decimal operation
Any (retained)
Not affected
Any (reset)
Not affected
Retains previous status
Retains previous status
Modified
Not modified
Comparison
SKE SKNE SKGE SKLT
m, #n4 m, #n4 m, #n4 m, #n4 r, m m, r m, #n4 @r, m m, @r
Any (retained)
Any (retained)
Not affected
Retains previous status
Retains previous status
Modified
Not modified
Transfer
LD ST MOV
Any (retained)
Any (retained)
Not affected
Retains previous status
Retains previous status
Modified
Not modified
Modified
Rotation
RORC r
Any (retained)
Any (retained)
Not affected
Value of b0 of general register
Retains previous status
Not modified
Not modified
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Table 7-2. Modification of Data Memory Address and Modification of Indirect Transfer Address by Index Register and Data Memory Row Address Pointer
General Register Address Specified by r
Data Memory Address Specified by m Bank Row Address Column Address
Indirect Transfer Address Specified by @r
IXE
MPE
Bank
Row Address
Column Address
Bank
Row Address
Column Address
b3 b2 b1 b0 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b2 b1 b0 b3 b2 b1 b0 b3
0
0
RP
r
BANK
m
BANK
mR
(r)
0
1
ditto
ditto
MP
(r)
BANK 1 0 ditto Logical IX
m OR
BANK Logical IXH, IXM
mR OR (r)
1
1
ditto
ditto
MP
(r)
BANK IX IXE
: bank register : index register : index enable flag
IXH : bits 10 through 8 of index register IXM : bits 7 through 4 of index register IXL m mR mC MP r RP (x) : bits 3 through 0 of index register : data memory address indicated by mR, mC : data memory row address (high) : data memory column address (low) : data memory row address pointer : general register column address : general register pointer : contents addressed by x x : direct address such as m and r
MPE : memory pointer enable flag
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Table 7-3. Decimal Adjustment Data
Operation Result 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Hexadecimal Addition CY 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Decimal Addition Operation Result 0000B 0001B 0010B 0011B 0100B 0101B 0110B 0111B 1000B 1001B 0000B 0001B 0010B 0011B 0100B 0101B 0110B 0111B 1000B 1001B 1110B 1111B 1100B 1101B 1110B 1111B 1100B 1101B 1010B 1011B 1100B 1101B Operation Result 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 -16 -15 -14 -13 -12 -11 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 Hexadecimal Addition CY 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Operation Result 0000B 0001B 0010B 0011B 0100B 0101B 0110B 0111B 1000B 1001B 1010B 1011B 1100B 1101B 1110B 1111B 0000B 0001B 0010B 0011B 0100B 0101B 0110B 0111B 1000B 1001B 1010B 1011B 1100B 1101B 1110B 1111B Decimal Addition CY 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Operation Result 0000B 0001B 0010B 0011B 0100B 0101B 0110B 0111B 1000B 1001B 1100B 1101B 1110B 1111B 1100B 1101B 1110B 1111B 1100B 1101B 1110B 1111B 0000B 0001B 0010B 0011B 0100B 0101B 0110B 0111B 1000B 1001B
Operation Result CY 0000B 0001B 0010B 0011B 0100B 0101B 0110B 0111B 1000B 1001B 1010B 1011B 1100B 1101B 1110B 1111B 0000B 0001B 0010B 0011B 0100B 0101B 0110B 0111B 1000B 1001B 1010B 1011B 1100B 1101B 1110B 1111B 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Remark Decimal adjustment is not carried out correctly in the portion
in the above table.
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7.4 Notes on Using ALU
7.4.1 Notes on operation to program status word When an arithmetic operation is executed to the program status word, the result of the operation is stored to the program status word. The CY and Z flags of the program status word are normally set or reset depending on the result of an arithmetic operation. If an arithmetic operation is executed to the program status word itself, however, the result of the operation is stored to the program status word, and occurrence of a carry or borrow, and whether the result of the operation is zero cannot be identified. If the CMP flag is set, the result of the operation is not stored to the program status word, and therefore, the CY and Z flags are set or reset as usual. 7.4.2 Notes on using decimal operation A decimal operation can be executed as long as the result falls within the following ranges: (1) Result of addition must be 0 to 19 in decimal. (2) Result of subtraction must be 0 to 9 or -10 to -1 in decimal. If these ranges are exceeded in decimal operation, the CY flag is set, and the result of the operation is greater than 1010B (0AH).
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8. REGISTER FILE (RF) 8.1 Outline of Register File
Figure 8-1 outlines the register file. As shown in this figure, the register file consists of a control register that exists on a space different from the data memory, and a portion overlapping the data memory. The control register sets the conditions of the peripheral hardware. The data on the register file is read or data is written to the register file via window register. Figure 8-1. Outline of Register File
Register file 0 Control register (space different from data memory) Peripheral hardware
1
2 Row address
3
4
(same space as data memory) Data manipulation via window register
5
6
7 System register Window register
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8.2 Configuration and Function of Register File
Figure 8-2 shows the configuration of the register file and the relation between the data memory and register file. The register file is allocated addresses in 4-bit units in the same manner as the data memory, and has a total of 128 nibbles with row addresses 0H through 7H and column addresses 0H through 0FH. An area consisting of addresses 00H through 3FH is called a control register. This register sets the condition of the peripheral hardware. Addresses 40H through 7FH overlap the data memory. This means that the memory addresses 40H through 7FH of the bank of the data memory selected at that time exist at the addresses 40H through 7FH of the register file. Therefore, because addresses 40H through 7FH overlap the data memory, they can be treated in the same manner as an data memory area, except that they can be manipulated by using a register file manipulation instruction "PEEK WR, rf" or "POKE rf, WR"). Figure 8-2. Configuration of Register File and Relation with Data Memory
Column address 0 0 1
Row address
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
Data memory
2 3 4 5 6 7 BANK0 BANK1 BANK2 BANK3 System register
0 1 Control register 2 3 Register file
8.2.1 Register file manipulation instructions ("PEEK WR, rf", "POKE rf, WR") Data is read from or written to the register file via the window register of the system register, by using the following instructions: (1) "PEEK WR, rf" This instruction reads data from the register file addressed by "rf" to the window register. (2) "POKE rf, WR" This instruction writes data of the window register to the register file addressed by "rf".
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8.3 Control Registers
Figure 8-3 shows the configuration of the control registers. As shown in this figure, the control registers consist of a total of 64 nibbles (64 words x 4 bits) of addresses 00H through 3FH of the register file. Of these 64 nibbles, however, only 41 nibbles are actually used, and the remaining 23 nibbles are unused registers which are prohibited from reading or writing. Each nibble of a control register has an attribute which may be read/write (R/W), read-only (R), write-only (W), or reset on read (R & Reset). Nothing is affected even if data is written to read-only (R and R & Reset) registers. If a write-only register (W) is read, an "undefined" value is read. The bits fixed to "0" of the 4-bit data in 1 nibble are always "0" when they are read, and retain "0" even when data is written to them. If an attempt is made to read the contents of the unused 23 nibbles, an undefined value is read. Nothing is changed even if data is written to these nibbles.
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Figure 8-3. Configuration of Control Register (1/2)
Column Address Row Address Item 0 1 Stack pointer Name SP
< < < <
2 Serial I/O1 mode select (SIO1MODE) S I O 1 C K 1 S I O 1 C K 0
3
4
IF counter open status judge (IFCGOSTR)
5 PLL unlock FF judge
(PLLULJDG)
6
A/D converter compare judge (ADCJDG)
7 CE pin level judge (CEJDG) C E 0 0
0 (8)Note Symbol
SS SSSSI I PPPPOO 321011 TH SI Z
> > >
0
0
I F C 0G0 O S T T R
0
P L L 0U0 L
0
A D C 0C0 M P
>
Read/ Write
R/W
R/W
R & Reset
R Key input judge (KEYJDG)
R
Basic timer 0 carry FF judge (BTM0CYJG)
Name
LCD mode LCD port IF counter PWM mode A/D converter PLL unlock channel select FF sensibility select select mode select select select (LCDMODE) (LCDPORT) (IFCMODE) (PWMMODE) (ADCCH) (PLLULSEN) K S E 0N L C D E N P 0 Y S E L P 0 X S E L P 0 E S E L P 0 F S E L I F C M D 1 I F C M D 0 I F C C K 1 I F C C K 0 P W M 2 S E L P W M 1 S E L P W M 0 S E L C G P S E L A D C C H 3 A D C C H 2 A D C C H 1 A D C C H 0 P L U L S E N 3 P L U L S E N 2 P L U L S E N 1
1 (9)Note Symbol
0
P L U L0 S E N 0
0
K E Y 0J0
0
B T M 00 C Y
Read/ Write
R/W
R/W PLL mode select (PLLMODE) P L L M D 3 P L L M D 2 P L L M D 1 P L L M D 0
R/W
R/W IF counter control (IFCCONT) I F C 0S T R T I F C R E S
R/W
R/W
R & Reset
R & Reset
Port 0C group l/O select (P0CGPIO)
Name
2 (A)Note Symbol
0
0
0
P 0 C 0G I O
Read/ Write
R/W
PLL reference clock select (PLLRFCLK)
R/W
R/W Port 1A Port 0B Port 0A bit l/O select bit l/O select bit l/O select (P1ABIO) (P0BBIO) (P0ABIO) P 1 A B I O 3 P 1 A B I O 2 P 1 A B I O 1 P 1 A B I O 0 P 0 B B I O 3 P 0 B B I O 2 P 0 B B I O 1 P 0 B B I O 0 P 0 A B I O 3 P 0 A B I O 2 P 0 A B I O 1 P 0 A B I O 0
Name
3 (B)Note Symbol
P L L R F C K 3
P L L R F C K 2
P L L R F C K 1
P L L R F C K 0
Read/ Write
R/W
R/W
R/W
R/W
Note
( ) indicates the address when the assembler (AS17K) is used.
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PD17010
Figure 8-3. Configuration of Control Register (2/2)
8
9
A
B
C
D
E
F
Serial l/O0 Basic timer mode select clock select (SIO0MODE) (BTMCLK) SSSSBB IBI ITT O OOMM 0 0011 C MTCC H SXKK 10 B T M 0 C K 1 B T M 0 C K 0
Timer counter Timer counter 12-bit timer Interrupt overflow clock select mode control group select detect (TMCLK) (TMMDCONT) (IGRPSELR)
(TMOVDET)
T M C K 3
T M C K 2
T M C K 1
T M C K0 0
0
T T M M R O 0V0P T F
T M R E S
T M E N0
0
I G R 0P S L
R/W Serial I/O0 wait control (SIO0WT) S B A C K S I O 0 N W T S I O 0 W R Q 1
R/W
Serial l/O0 wait status judge (SIO0WSTR)
R/W
R
R/W
R/W Interrupt edge select (INTEDGE) II EE GG 010
S I O 000 W R Q 0 R
S I O 00 W S T T
0
R/W Serial I/O0 status judge (SIO0STUS) S I O 0 S F 8 S I O 0 S F 9 S B S T T S B B S Y
R/W Interrupt Interrupt permission 1 permission 2 (INTPM1) (INTPM2) IIIIII PPPPPP ISBTG0 0F I TMR COM P 01
0
R/W Serial l/O0 interrupt mode (SIO0INT) SSSS IIII OOOO 0000 IIII MMMM DDDD 3210 R/W Serial l/O0 clock select (SIO0CLK) S I O 0 C K 3 S I O 0 C K 2 S I O 0 C K 1 S I O 0 C K 0 IF counter Serial I/O0 Basic timer 12-bit timer interrupt interrupt 1 interrupt interrupt request request request request (IREQIFC) (IREQSIO0) (IREQBTM1) (IREQTM) I I I I R R R R Q Q Q Q 000I000S000B000T F I T M C O M 0 1
R/W
R/W
Group INT0 interrupt interrupt request request (IREQGRP) (IREQINT) I II I N RN R T QT Q 100G0000 R P
R/W
R/W
R/W
R/W
R/W
R/W
R/W
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PD17010
Table 8-1. Outline of Peripheral Hardware Control Function of Control Register (1/5)
Peripheral Hardware Name Control Register Address Read/ b3 Write b2 Symbol b1 b0 Stack Stack pointer 01H R/W (SP3) ---------------(SP2) ---------------- Stack pointer (SP1) ---------------(SP0) BTM1CK1 ---------------- Sets basic timer 1 interrupt time BTM1CK0 ---------------BTM0CK1 ---------------- Sets basic timer 0 carry FF time BTM0CK0 0CH R/W TMCK3 0 ---------------TMCK2 0 ---------------TMCK1 ---------------- Sets clock of 12-bit timer TMCK0 0DH R 0 ---------------0 ---------------0 0 0 1 1 1 kHz 3 kHz 100 kHz 90 kHz 0 1 0 1 0 0 Retained 0 0 1 100 ms 250 ms 5 ms 1 1 ms 7 7 7 Peripheral Hardware Control Function Functional Outline Set Value On Reset Power- Clock ON Stop CE
SP Timer Basic timer clock select (BTMCLK) Timer counter clock select (TMCLK) Timer counter overflow detect (TMOVDET) 09H R/W
0
0
Retained
0 1 0 1 -----------------------------------------0 0 1 1 100 ms 250 ms 5 ms 0 1 0 1 ms 1
---------------TMOVF Detects overflow of timer counter Set on occurrence of overflow. Reset by reset signal. 0 0 Retained
12-bit timer mode control
0EH
R/W
0 ---------------TMRPT ---------------TMRES Resets data of timer/counter. ---------------0: NOP instruction 1: Reset Sets operation mode of 12-bit timer. 0: Free-run count mode 1: Modulo count mode 0 0 Retained
(TMMDCONT) Basic timer 0 carry FF judge (BTM0CYJG) Pin CE pin level judge 07H R 17H
TMEN Read 0 ---------------& 0 ----------------
Sets operation of timer/counter. 0: Does not operate 1: Operates
Reset 0 ---------------BTM0CY 0 ---------------0 ---------------0 ---------------Detects basic timer 0 carry FF 0: Resets FF 1: Sets FF 0 1 1
(CEJDG)
CE
Detects status of CE pin
0: Low level 1: high level
--
--
--
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PD17010
Table 8-1. Outline of Peripheral Hardware Control Function of Control Register (2/5)
Peripheral Hardware Name Control Register Address Read/ b3 Write b2 Symbol b1 b0 Interrupt Interrupt group select 0FH R/W 0 ---------------0 ---------------0 ---------------IGRPSL Sets set condition of IRQGRP Peripheral Hardware Control Function Functional Outline Set Value On Reset Power- Clock ON Stop CE
(IGRPSELR)
0: Edge of INT1 pin 1: Timer overflow
0
0
0
Interrupt edge select
1FH
R/W
(INTEDGE) Interrupt permission 1 2EH R/W
0 ---------------0 ---------------IEG1 Sets interrupt issuance edge of 0: Rising edge 1: Falling edge ---------------IEG2 INT1 and INT0 pins 0 ---------------0 ---------------IPIFC Enables IF counter, serial ---------------IPSIO0 interface 0, basic timer 1, IPBTM1 12-bit timer, INT1 pin or ---------------IPTM overflow of timer/counter, and ---------------IRGRP INT0 pin interrupts ---------------IP0 0 ---------------0 ---------------0 ---------------IRQIFC Detects interrupt request of IF counter
0
0
0
(INTPM1) Interrupt permission 2 2FH R/W
0: Disabled
1: Enabled
0
0
0
(INTPM2) IF counter interrupt request (IREQIFC) 3AH R/W
0: No request
1: Request
0
0
0
Serial I/O0 interrupt request (IREQSIO0)
3BH
R/W
0 ---------------0 ---------------0 ---------------IRQSIO0 Detects interrupt request of serial interface 0
0: No request
1: Request
0
0
0
Basic timer 1 interrupt request (IREQBTM1)
3CH
R/W
0 ---------------0 ---------------0 ---------------IRQBTM1 Detects interrupt request of basic timer 1
0: No request
1: Request
0
0
0
12-bit timer interrupt request (IREQTM)
3DH
R/W
0 ---------------0 ---------------0 ---------------IRQTM Detects interrupt request of 12-bit timer
0: No request
1: Request
0
0
0
Group interrupt request (IREQGRP)
3EH
R/W
INT1 Detects status of INT1 pin 0: Low level ---------------0 ---------------0 ---------------IRQGRP Detects INT1 pin or timer/counter overflow interrupt request 0: No request 0: Low level
1: High level
0
0
0
1: Request 1: High level 0 0 0
INT0 interrupt request (IREQINT0)
3FH
R/W
INT0 Detects status of INT0 pin ---------------0 ---------------0 ---------------IRQ0 Detects interrupt request of INT0 pin
0: No request
1: Request
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PD17010
Table 8-1. Outline of Peripheral Hardware Control Function of Control Register (3/5)
Peripheral Hardware Name Control Register Address Read/ b3 Write b2 Symbol b1 b0 PLL frequency synthe- (PLLULJDG) sizer PLL unlock FF sensibility select (PLLULSEN) PLL mode select 21H R/W 15H PLL unlock FF judge 05H Read 0 ---------------& 0 ---------------Reset 0 ---------------PLLUL Detects status of unlock FF R/W Peripheral Hardware Control Function Functional Outline Set Value On Reset Power- Clock ON Stop CE
Un0: Locked 1: Unlocked
Re-
Retained
defined tained
PLULSEN3 0 ---------------PLULSEN2 0 ---------------0 PLULSEN1 ---------------- Sets set delay time of unlock FF 1 s PLULSEN0 0 PLLMD3 0 ---------------PLLMD2 0 ---------------PLLMD1 ---------------- Sets division method of PLL PLLMD0 PLLRFCK3 ---------------PLLRFCK2 Sets reference frequency of ---------------PLLRFCK1 PLL ---------------PLLRFCK0 ADCCH3 0 ---------------ADCCH2 ---------------ADCCH1 Selects pin used as A/D ---------------ADCCH0 converter 0 ---------------0 ---------------0 ---------------ADCCMP Detects comparison result of A/D converter
0 2 s 1
1 1 0.5 s Disable 0 1
0
0
Retained
(PLLMODE) PLL reference clock select (PLLRFCLK) A/D A/D con14H R/W 31H R/W
0 0 Disable MF 0 1 0:1.25 4:6.25 8:3 C:1 1:2.5 5:12.5
1 VHF 0 2:5 6:25
1 HF 1 3:10 7:50
0 F
0 F
Retained Retained
9:A:B:Setting prohibited D:9 E:100 F:Off
converter verter channel select (ADCCH) A/D converter compare judge (ADCJDG) 06H R
0:AD0 4:AD4
1:AD1 5:AD5
2:AD2 3:AD3 6:7:Input port
7
7
7
0:VREF>VADCIN
1: VREFUn-
Re-
Retained
defined tained
General- Port 0C purpose group I/O port select (P0CGPIO) Port 1A bit I/O select
27H
R/W
0 ---------------0 ---------------0 Sets I/O mode of ---------------P0CGIO P0C3-P0C0 pins (in 4-bit units) P1ABIO3 ---------------P1ABIO2 ---------------P1ABIO1 ---------------P1ABIO0 Sets I/O mode of P1A3, P1A2, P1A1, P1A0, P0B3, P0B2, P0B1, P0B0, P0A3, P0A2, P0A1, and P0A0 pins
0: Input 1: Output 0: Input 1: Output
0 0
0 0
0 0
35H
R/W
(P1ABIO) Port 0B bit I/O select 36H R/W
(P0BBIO) Port 0A bit I/O select 37H R/W
P0BBIO3 (in 1-bit units) ---------------P0BBIO2 ---------------P0BBIO1 ---------------P0BBIO0 P0ABIO3 ---------------P0ABIO2 ---------------P0ABIO1 ---------------P0ABIO0 PWM2SEL Sets PWM2, PWM1, and PWM0 0: General-purpose output port ---------------PWM1SEL pins as D/A converter. 1: D/A converter ---------------PWM0SEL --------------------------------------------------------CGPSEL Sets CGP pin as CGP 0: General-purpose output port 1: CGP 0 0 Retained
(P0ABIO) D/A PWM mode 13H R/W
converter select
(PWMMODE)
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PD17010
Table 8-1. Outline of Peripheral Hardware Control Function of Control Register (4/5)
Peripheral Hardware Name Control Register Address Read/ b3 Write b2 Symbol b1 b0 Serial Serial I/O1 02H R/W SIO1TS Starts serial interface 1. 0: Does not operate 1: Starts --------------------------------------------------------SIO1HIZ Sets P0B1/SO1 pin. 0: General-purpose port 1: Serial out --------------------------------------------------------0 0 1 1 SIO1CK1 External 37.5 kHz 75 kHz 450 kHz ---------------- Sets clock of serial interface 1 SIO1CK0 0 1 0 1 0 0 1 1 R/W SIO0CH Sets 2-line or 3-line mode. 2-line I2C bus 3-line Setting ---------------serial I/O serial I/O prohibited SB Sets I2C bus/serial I/O mode. 0 1 0 1 --------------------------------------------------------SIO0MS Sets direction of clock. 0: External clock 1: Internal clock --------------------------------------------------------SIO0TX Sets I/O mode. 0: Input 1: Output SBACK ---------------SIO0NWT ---------------SIO0WRQ1 ---------------SIO0WRQ0 Sets and detects acknowledge in I2C bus mode. Enables wait. Sets wait timing of serial interface 0 Setting and detecting of 0, 1 -----------------------------------------0: Enabled 1: Disabled -----------------------------------------0 0 1 1
No wait 8 clocks 9 clocks SB8 clocks
Peripheral Hardware Control Function Functional Outline Set Value
On Reset Power- Clock ON Stop CE
0
0
0
interface mode select
(PLLULJDG) Serial I/O0 mode select 08H
0
0
0
(SIO0MODE) Serial I/O0 wait control 18H
R/W
0
0
0
(SIO0WT) Serial I/O0 wait status judge (SIO0WSTR) 19H R
0
1
0
1
0 ---------------0 ---------------0 ---------------SIO0WSTT Detects wait status of serial interface 0
0: Wait 1: Serial communication
0
0
0
Serial I/O0 status judge
28H
R/W
SIO0SF8 ---------------SIO0SF9 interface 0 Detects clock counter of serial
Set when clock counter is 8; reset when clock counter is 0 or 1 Set when clock counter is 9;
0
0
0
reset when clock counter is 0 or 1 --------------------------------------------------------SBSTT Detects number of clocks in I2C Set when start condition bus mode ---------------SBBSY Detects start and stop conditions in I2C bus mode Serial I/O0 interrupt mode (SIO0INT) Serial I/O0 clock select 39H R/W 38H R/W SIO0IMD3 ---------------SIO0IMD2 ---------------SIO0IMD1 ---------------SIO0IMD0 SIO0CK3 ---------------SIO0CK2 ---------------SIO0CK1 ---------------SIO0CK0 0 0 Sets interrupt condition of serial interface 0 0 0 Sets internal clock of serial interface 0 0 0 37.5 kHz 75 kHz 0 1 1 1 UnReRetained 112.5 kHz 225 kHz defined tained 0 1 9 th clock -----------------------------------------Sets when start condition stop condition 0 7th clock 0 0 7th clock after start condition 0 0 8th clock 1 0 ReRetained Stop condition Undefined tained 1
(SIO0STUS)
(SIO0CLK) FreIF counter 04H R
quency open status counter judge (IFCGOSTR)
0 ---------------0 ---------------0 ---------------IFCGOSTT Detects gate opening/closing of 0: Close 1: Open frequency counter 0 0 1 1 CGP FMIF AMIF FCG 0 1 0 1 -----------------------------------------0 1ms 0 4 ms 1 8 ms 1 Open 0 1kHz 1 100 kHz 1 900 kHz 1
0 0
-- 0
-- Retained
IF counter mode select
12H
R/W
(IFCMODE) IF counter control 23H R/W
IFCMD1 ---------------- Sets mode of frequency counter IFCMD0 ---------------IFCCK1 ---------------- Sets gate time of frequency IFCCK0 counter 0 ---------------0 ---------------IFCSTRT Specifies count start of ---------------IFCRES Specifies data reset of frequency counter.
0
0
Retained
0: NOP instruction 1: Start 0: NOP Instruction 1: Reset
(IFCCONT)
frequency counter.
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PD17010
Table 8-1. Outline of Peripheral Hardware Control Function of Control Register (5/5)
Peripheral Hardware Name Control Register Address Read/ b3 Write b2 Symbol b1 b0 LCD driver LCD mode select 10H R/W 0 ---------------0 ---------------KSEN Sets key source signal output ---------------LCDEN Sets LCD display output 0 0 Retained Peripheral Hardware Control Function Functional Outline Set Value On Reset Power- Clock ON Stop CE
0: Key source off 1: Key source on 0: Display off 1: Display on 0 0 Retained
(LCDMODE) LCD port select 11H R/W
(LCDPORT) Key input judge 16H
R0YSEL Sets P0Y0-P0Y15, P0X0-P0X5, 0: LCD segment ---------------R0XSEL P0E0-P0E3, and P0F0-P0F3 pins 1: General-purpose output port ---------------R0ESEL as general-purpose output port ---------------R0FSEL
(KEYJDG)
Read 0 ---------------& 0 ---------------Reset 0 ---------------KEYJ Detects key input latch of LCD key source
0: Not latched
1: Latched
0
0
0
8.4 Notes on Using Register File
Remember the following three points, (1) through (3), when manipulating the write-only registers (W), read-only registers (R), and unused registers of the control registers (addresses 00H through 3FH of the register file): (1) When a write-only register is read, an "undefined value" is read. (2) Nothing is changed even if data is written to a read-only register. (3) An "undefined value" is read if an unused portion is read. Nothing is changed even if data is written to this portion.
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PD17010
9. DATA BUFFER (DBF) 9.1 Outline of Data Buffer
Figure 9-1 outlines the data buffer. The data buffer is located on the data memory and has the following two functions: (1) Reads constant data on program memory (table reference) (2) Transfers data with peripheral hardware Figure 9-1. Outline of Data Buffer
Data buffer
Writes data (PUT) Table reference (MOVT)
Reads data (GET)
Peripheral hardware
Constant data
Program memory
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PD17010
9.2 Data Buffer
9.2.1 Configuration of data buffer Figure 9-2 shows the configuration of the data buffer. As shown in this figure, the data buffer consists of a total of 16 bits at addresses 0CH through 0FH of BANK0 on the data memory. The MSB of the 16-bit data is the bit b3 of address 0CH, and the LSB is the bit b0 of address 0FH. Because the data buffer is located on the data memory, it can be manipulated by any data memory manipulation instruction. Figure 9-2. Configuration of Data Buffer
Column address 0 0 1
Row address
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
Data buffer (DBF) 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 System register BANK0 BANK1 BANK2 BANK3 Data memory
2 3 4 5 6 7
Address Data Memory Bit Bit Symbol
>
0 CH
0 DH
0 ED
0 FH
b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 DBF 3 M DBF 2 DBF 1 DBF 0
>
Data buffer Data
L S Data
<
S
<
B
B
70
PD17010
9.2.2 Table reference instruction ("MOVT DBF, @AR") The operation of the "MOVT DBF, @AR" instruction is described next. When the table reference instruction is executed, one stack level is used. All the program memory addresses, 0000H through 1EFBH, can be referenced. MOVT DBF, @AR This instruction reads the contents of the program memory addressed by the contents of the address register to the data buffer. 9.2.3 Peripheral hardware control instructions ("PUT", "GET") The operations of the "PUT" and "GET" instructions are described next. (1) GET DBF, p Reads the data of the peripheral register addressed by p to the data buffer. (2) PUT p, DBF Sets the data of the data buffer to the peripheral register addressed by p.
9.3 List of Peripheral Hardware and Data Buffer Functions
Table 9-1 lists the functions of the peripheral hardware and data buffer.
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PD17010
Table 9-1. List of Peripheral Hardware and Data Buffer Functions (1/2)
Peripheral Register Transferring Data with Data Buffer Peripheral Hardware Name Symbol Peripheral Execution of PUT/ Address A/D converter Serial interface Serial interface 1 (SIO1) Serial interface 0 (I C, SBI, SIO0) D/A converter (PWM output) PWM0 pin PWM1 pin PWM2 pin LCD controller/driver LCD segment group 0 LCD segment group 1 LCD segment group 2 LCD segment group 3 LCD segment group 4 LCD segment group 5 LCD segment group 6 LCD segment group 7 Output port Port 0X Port 0Y Clock generator port (CGP) Address register (AR) PLL frequency synthesizer Key source controller/decoder Frequency counter 12-bit timer Timer modulo Timer counter PWM data register 0 PWM data register 1 PWM data register 2 LCD segment group register 0 LCD segment group register 1 LCD segment group register 2 LCD segment group register 3 LCD segment group register 4 LCD segment group register 5 LCD segment group register 6 LCD segment group register 7 P0X group register P0Y group register CGP data register Address register PLL data register Key source data register IF counter data register Timer modulo register Timer counter PWMR0 PWMR1 PWMR2 LCDR0 LCDR1 LCDR2 LCDR3 LCDR4 LCDR5 LCDR6 LCDR7 P0X P0Y CGPR AR PLLR KSR IFC TMM TMC 05H 06H 07H 08H 09H PUT PUT/GET
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------2
GET Instruction PUT/GET PUT/GET
A/D converter data register Presettable shift register 1
ADCR SIO1SFR
02H 03H
Presettable shift register 0
SIO0SFR
04H
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
0AH 0BH
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
0CH 0DH 0EH 0FH 0CH 42H 20H 40H 41H 42H 43H 46H 47H PUT PUT/GET PUT/GET PUT/GET PUT/GET PUT/GET GET PUT/GET GET
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
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PD17010
Table 9-1. List of Peripheral Hardware and Data Buffer Functions (2/2)
Function Number of I/O Bits Actual Number of Data Buffer of Bits x-0.5 x VDD, 1x63 64 Outline
8
6
Sets compare voltage VREF data of A/D converter
VREF =
8 8
8 8
Sets serial out data and reads serial in data Sets duty factor of output signal of D/A converter Duty D = x+0.25 x 100%, 0x1125 256
Frequency f = 4349.5 Hz 8
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
7
LCD segment group 0 LCD segment group 1 LCD segment group 2 LCD segment group 3 LCD segment group 4 LCD segment group 5 LCD segment group 6 LCD segment group 7 Sets output data of port 0X 0: low level, 1: high level Sets output data of port 0Y 0: low level, 1: high level Sets frequency of SG function 18 kHz 2 (2xx) Sets duty factor of VDP function Frequency f = Duty D = x+2 , 0x63 67 Sets display data of each group 0: Display on 1: Display off
4 7 7 7 3 7 7
8 16 8
8 16 7
16 16 16 16 16 16
16 16 16 16 12 12
Transfers data with address register Sets division value (N value) of PLL Sets output data of key source signal Reads measured value of frequency counter Sets reference data of timer modulo Sets data of up counter
73
PD17010
9.4 Notes on Using Data Buffer
Remember the following three points when transferring data with the peripheral hardware via data buffer by executing the PUT instruction to access the unused peripheral address or write-only peripheral register or the GET instruction to access the read-only peripheral register: (1) An "undefined value" is read when a write-only register is read. (2) Nothing is changed even if data is written to a read-only register. (3) An "undefined value" is read if an unused address is read. Nothing is changed even if data is written to this address.
74
PD17010
10. INTERRUPT 10.1 Outline of Interrupt Block
Figure 10-1 outlines the interrupt block. As shown in this figure, the interrupt block temporarily stops the program under execution and branches execution to an interrupt vector address when an interrupt request is output by peripheral hardware. The interrupt block consists of an "interrupt control block" for each peripheral hardware, "interrupt enable flip-flop" that enables all interrupts, "stack pointer" that is controlled when an interrupt has been accepted, "address stack register", "program counter", and "system register stack". The "interrupt control block" of each peripheral hardware consists of an "interrupt request flag (IRQxxx) that detects each interrupt request", "interrupt permission flag (IPxxx) that enables each interrupt", and "vector address generator (VAG)" that specifies each vector address when an interrupt has been accepted. The following peripheral hardware has an interrupt function: * INT0 pin * Group (INT1 pin or timer/counter overflow) * 12-bit timer * Basic timer 1 * Serial interface 0 * Frequency counter
75
PD17010
Figure 10-1. Outline of Interrupt Block
Interrupt control block IPIFC flag Frequency counter lRQIFC flag
Vector address generator 01H
Program counter
Stack pointer
Address stack register
IPSIO0 flag Serial interface 0 IRQSIO0 flag
Vector address generator 02H
System register IPBTM1 flag Basic timer 1 IRQBTM1 flag
Vector address generator 03H
Interrupt stack register
IPTM flag 12-bit timer IRQTM flag
Vector address generator 04H
INT1 pin or timer/ counter overflow
IPGRP flag IRQGRP flag
Vector address generator 05H
IP0 flag INT0 pin IRQ0 flag
Vector address generator 06H
El, DI instructions
Interrupt enable flip-flop
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PD17010
10.2 Interrupt Control Block
The interrupt control block is provided to each peripheral hardware and detects an interrupt request, enables the interrupt, and generates a vector address when the interrupt has been accepted. 10.2.1 Configuration and function of interrupt request flag (IRQxxx) The interrupt request flag (IRQxxx) is set to "1" when an interrupt request is issued from the corresponding peripheral hardware, and is reset to "0" when the interrupt has been accepted. If an interrupt is not enabled, the status of issuance of each interrupt request can be detected by detecting the interrupt request flag (IRQxxx). When "1" is directly written to an interrupt request flag via window register, the operation is equivalent to issuance of an interrupt request. Once this flag has been set to "1", it is not reset until the corresponding interrupt is accepted or "0" is written to it via the window register. If two or more interrupt requests are issued at the same time, the interrupt request flag corresponding to the interrupt that is not accepted is not reset. The configuration and function of the interrupt request flag are illustrated below.
Flag Symbol Name b3 b2 b1 b0 I R Q I F C Address
Read/ Write
IF counter interrupt request register (lREQIFC)
0
0
0
3AH
R/W
Sets status of issuance of frequency counter interrupt request 0 1 Interrupt request not issued Interrupt request issued
Fixed to "0"
On reset
Power-ON Clock stop CE
0
0
0
0 0 0
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PD17010
Flag Symbol Name b3 b2 b1 b0 I R Q S I O 0 Address
Read/ Write
Serial I/O0 interrupt request register (IREQSIO0)
0
0
0
3BH
R/W
Sets status of issuance of serial interface 0 interrupt request 0 1 Interrupt request not issued Interrupt request issued
Fixed to "0"
On reset
Power-ON Clock stop CE
0
0
0
0 0 0
Flag Symbol Name b3 Basic timer 1 interrupt request register (IREQBTM1) b2 b1 b0 I R Q B T M 1 Address
Read/ Write
0
0
0
3CH
R/W
Sets status of issuance of basic timer 1 interrupt request 0 1 Interrupt request not issued Interrupt request issued
Fixed to "0"
On reset
Power-ON Clock stop CE
0
0
0
0 0 0
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PD17010
Flag Symbol Name b3 12-bit timer interrupt request register (IREQTM) b2 b1 b0 I R Q T M Address
Read/ Write
0
0
0
3DH
R/W
Sets status of issuance of 12-bit timer interrupt request 0 1 Interrupt request not issued Interrupt request issued
Fixed to "0"
On reset
Power-ON Clock stop CE
0
0
0
0 0 0
Flag Symbol Name b3 Group interrupt request register (IREQGRP) I N T 1 b2 b1 b0 I R Q G R P Address
Read/ Write
0
0
3EH
R/W
Sets status of issuance of INT1 pin or timer/counter overflow interrupt request 0 1 Interrupt request not issued Interrupt request issued
Fixed to "0"
Detects status of INT1 pin 0 1 Low level is input High level is input
On reset
Power-ON Clock stop CE
0 0 0
0
0
0 0 0
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PD17010
Flag Symbol Name b3 I N T 0 b2 b1 b0 I R Q 0 Address
Read/ Write
INT0 interrupt request register (IREQINT0)
0
0
3FH
R/W
Sets status of INT0 pin interrupt request issuance 0 1 Interrupt request not issued Interrupt request issued
Fixed to "0"
Detects status of INT1 pin 0 1 Low level is input High level is input
On reset
Power-ON Clock stop CE
0 0 0
0
0
0 0 0
80
PD17010
10.2.2 Configuration and function of interrupt permission flag (IPxxx) Each interrupt permission flag enables the interrupt of each peripheral hardware. So that an interrupt is accepted, all the following three conditions must be satisfied: * Interrupt is enabled by corresponding interrupt permission flag. * Interrupt request is issued by corresponding interrupt request flag. * "EI" instruction (that enables all interrupts) is executed. The configuration and function of the interrupt permission flag are illustrated below.
Flag Symbol Name b3 b2 b1 I P I F C b0 I P S I O 0 Address
Read/ Write
Interrupt permission 1 register (INTPM1)
0
0
2EH
R/W
Enables serial I/O0 interrupt 0 1 Disables Enables
Enables IF counter interrupt 0 1 Disables Enables
Fixed to "0"
On reset
Power-ON Clock stop CE
0
0
0 0 0
0 0 0
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PD17010
Flag Symbol Name b3 I P B T M 1 b2 I P T M b1 I P G R P b0 I P 0 Address
Read/ Write
Interrupt permission 2 register (INTPM2)
2FH
R/W
Enables INT0 pin interrupt 0 1 Disables Enables
Enables INT1 pin or timer/counter overflow interrupt 0 1 Disables Enables
Enables 12-bit timer interrupt 0 1 Disables Enables
Enables basic timer 1 interrupt 0 1 Disables Enables
On reset
Power-ON Clock stop CE
0 0 0
0 0 0
0 0 0
0 0 0
10.2.3 Vector address generator (VAG) The vector address generator generates a branch address (vector address) of the program memory corresponding to an interrupt source when each peripheral hardware interrupt has been accepted. Table 10-1 shows the vector addresses corresponding to the respective interrupt sources. Table 10-1. Vector Addresses Corresponding to Respective Interrupt Sources Interrupt Source INT0 pin INT1 pin or timer/counter overflow 12-bit timer Basic timer 1 Serial interface 0 Frequency counter Vector Address 06H 05H 04H 03H 02H 01H
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10.3 Interrupt Stack
10.3.1 Configuration and function of interrupt stack register Figure 10-2 shows the configuration of the interrupt stack register and the system registers that are saved to the interrupt stack register. To the interrupt stack register, the contents of the following system registers are saved when an interrupt has been accepted. * Window register (WR) * Bank register (BANK) * General register pointer (RP) * Program status word (PSWORD) When an interrupt has been accepted and the contents of the above system registers have been saved to the interrupt stack register, the contents of the system registers, except the window register, are reset to "0". The interrupt stack register can save up to three levels of the contents of the above system registers. Therefore, interrupts can be nested up to three levels. The contents of the interrupt stack register are restored to the system registers when the interrupt return instruction ("RETI") is executed. Figure 10-2. Configuration of Interrupt Stack Register
Interrupt Stack Register (lNTSK) Window stack (WRSK) b3 b2 b1 b0 b3 - - - Bank stack (BANKSK) b2 - - - b1 b0 Register pointer stack H (RPHSK) b3 - - - b2 - - - b1 b0 Register pointer stack L (RPLSK) b3 b2 b1 b0 Status stack (PSWSK) b3 b2 b1 b0
Name
Bit 0H 1H 2H
Remark -: Bit not saved
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10.3.2 Operation of interrupt stack register Figure 10-3 shows the operation of the interrupt stack register. When interrupts are nested exceeding four levels, the contents saved first are dumped and therefore, must be saved by program. Figure 10-3. Operation of Interrupt Stack Register (a) When interrupts are nested within 3 levels
Undefined Undefined Undefined
A
Undefined Undefined
B A
Undefined
A
Undefined Undefined
Undefined Undefined Undefined
On application Interrupt A of VDD
Interrupt B
RETI
RETI
(b) If interrupts are nested exceeding 3 levels
A
Undefined Undefined
B A
Undefined
C B A
D C B
C B B
B B B
B B B
Interrupt A
Interrupt B
Interrupt C
Interrupt D
RETI
RETI
RETI
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10.4 Stack Pointer, Address Stack Register, and Program Counter
The address stack register saves a return address from which program execution is resumed when execution has returned from an interrupt processing routine. The stack pointer specifies the address of an address stack register. When an interrupt has been accepted, the value of the stack pointer is decremented by one, and the value of the program counter at that time is saved to the address stack register specified by the stack pointer. When a dedicated return instruction "RETI" is executed after the processing of the interrupt processing routine has been completed, the contents of the address stack register specified by the stack pointer are restored to the program counter, and the value of the stack pointer is incremented by one. For more information, refer to 3. ADDRESS STACK (ASK).
10.5 Interrupt Enable Flip-Flop (INTE)
The interrupt enable flip-flop enables all the interrupts. When this flip-flop is set, all the interrupts are enabled. When it is reset, all the interrupts are disabled. To set or reset this flip-flop, a dedicated instruction, "EI (to set)" or "DI (to reset)", is used. The "EI" instruction sets this flip-flop when the next instruction is executed, and the "DI" instruction resets the flipflop during its execution. When an interrupt is accepted, this flip-flop is automatically reset. Even if the "DI" instruction is executed in the DI status, or if the "DI" instruction is executed in the EI status, nothing is affected. This flip-flop is reset at power-ON reset or CE reset, and when the clock stop instruction is executed.
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10.6 Accepting Interrupt
10.6.1 Accepting Interrupt and Priority An interrupt is accepted in the following sequence: (1) Each peripheral hardware outputs an interrupt request signal to the interrupt control block when an interrupt condition (for example, input of a falling edge to the INT0 pin) is satisfied. (2) When the interrupt control block accepts the interrupt request signal from the peripheral hardware, it sets the corresponding interrupt request flag (for example, IRQ0 flag for the INT0 pin) to "1". (3) If the interrupt permission flag (for example, IP0 flag for the IRQ0 flag) corresponding to the interrupt request flag that has been set to "1" when each interrupt request flag is set to "1", the interrupt control block outputs "1". (4) The signal output from the interrupt control block is ORed with the output of the interrupt enable flip-flop, and an interrupt accept signal is output. This interrupt enable flip-flop is set to "1" by the "EI" instruction and reset to "0" by the "DI" instruction. If the interrupt control block outputs "1" while the interrupt enable flip-flop is set to "1", the interrupt enable flip-flop outputs "1", and the interrupt is accepted. As shown in Figure 10-1, the output of the interrupt enable flip-flop is input to the interrupt control block via an AND circuit when the interrupt is accepted. The interrupt request flag is reset to "0" by the signal input to the interrupt control block, and a vector address for the interrupt is output. If the interrupt control block outputs "1" at this time, the interrupt accept signal is not transferred to the next stage. If two or more interrupt requests are issued at the same time, therefore, the interrupts are accepted according to the following priority: INT0 pin > INT1 pin or timer/counter overflow > timer > serial interface 1 > frequency counter If the interrupt permission flag is not set to "1", the interrupt generated by the corresponding source is not accepted. If the interrupt permission flag is reset to "0", therefore, the interrupt with a high hardware priority can be disabled.
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10.6.2 Timing chart illustrating acceptance of interrupt Figure 10-4 shows the timing chart illustrating how an interrupt is accepted. (1) in Figure 10-4 is the chart illustrating how one interrupt is accepted. (a) in (1) indicates the case where the interrupt request flag is set to "1" last, and (b) indicates the case where the interrupt permission flag is set to "1" last. In either case, the interrupt is accepted when all the interrupt request flag, interrupt enable flip-flop, and interrupt permission flag have been set to "1". If the flag or flip-flop that is set to 1 last in the first instruction cycle of the "MOVT DBF, @AR" instruction or when an instruction that satisfies a given skip condition is executed, the interrupt is accepted in the second instruction cycle of the "MOVT DBF, @AR" instruction or after the skipped instruction (treated as NOP) has been executed. The interrupt enable flip-flop is set in the instruction cycle next to the one in which the "EI" instruction was executed. (2) in Figure 10-4 is the timing chart illustrating how two or more interrupts are used. To use two or more interrupts, the interrupts are accepted according to the priority determined by hardware if all the interrupt permission flags are set. The hardware priority can be changed by manipulating the interrupt permission flag by program. The "interrupt cycle" shown in Figure 10-4 is a special cycle in which the interrupt request flag is reset after the interrupt has been accepted, a vector address is specified, and the contents of the program counter are saved. This cycle requires 4.44 s, which is equivalent to one instruction execution time. For details, refer to 10.7 Operation after Accepting Interrupt.
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Figure 10-4. Timing Charts Illustrating Acceptance of Interrupts (1/2) (1) When one interrupt (e.g., rising of INT0 pin) is used (a) If interrupt mask time is not specified by interrupt permission flag (IPxxx) <1> If a normal instruction other than "MOVT" and instruction that satisfies a skip condition is executed when interrupt is accepted
Instruction INTE INT0 pin IRQ0 flag IP0 flag
1 instruction cycle 4.44 s
EI
MOV POKE WR, #0001B INTPM1, WR
Normal instruction
Interrupt cycle
Interrupt enable period
Interrupt processing routine Interrupt accepted
<2> If "MOVT" or instruction that satisfies a skip condition is executed when interrupt is accepted
Instruction INTE INT0 pin IRQ0 flag IP0 flag Interrupt enable period Interrupt accepted
Interrupt processing routine
EI
MOV POKE WR, #0001B INTPM1, WR
MOVT DBF, @AR skip instruction
Interrupt cycle
(b) If interrupt pending period is specified by interrupt permission flag
Instruction INTE INT0 pin IRQ0 flag IP0 flag Interrupt enable period Interrupt processing routine Interrupt accepted EI
MOV POKE WR, #0001B INTPM1, WR Interrupt cycle
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Figure 10-4. Timing Charts Illustrating Acceptance of Interrupts (2/2) (2) When two or more interrupts (e.g., INT0 pin and INT1 pin) are used (a) Hardware priority
Instruction INTE INT0 pin IRQ0 flag INT1 pin IRQGRP flag IP0 flag IPGRP flag
MOV POKE WR, #0011B INTPM1, WR
EI
Interrupt cycle
EI
Interrupt cycle
INT0 pin interrupt pending period INT0 pin interrupt processing INT1 pin interrupt pending period INT0 pin interrupt accepted
INT1 pin interrupt processing INT1 pin interrupt accepted
(b) Software priority
Instruction INTE INT0 pin IRQ0 flag INT1 pin IRQGRP flag IP0 flag IPGRP flag
MOV POKE WR, #0010B INTPM1, WR
EI
Interrupt cycle
MOV POKE WR, #0011B INTPM1, WR
EI
Interrupt cycle
INT0 pin interrupt pending period INT1 pin interrupt pending period INT1 pin interrupt processing INT1 pin interrupt accepted
INT0 pin interrupt processing INT0 pin interrupt accepted
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10.7 Operation after Accepting Interrupt
When an interrupt has been accepted, the following processing is sequentially performed automatically: (1) The interrupt enable flip-flop and the interrupt request flag corresponding to the accepted interrupt request are reset to "0". The result is that the interrupt is disabled. (2) The contents of the stack pointer are decremented by one. (3) The contents of the program counter are saved to the address stack register specified by the stack pointer. The contents of the program counter are the program memory address to be executed next when the interrupt is accepted. For example, if a branch instruction is executed, the contents of the program counter are the branch destination address. If a subroutine call instruction is executed, they are the called address. If the skip condition of a skip instruction is satisfied, the next instruction is executed as "NOP" instruction, and then the interrupt is accepted. The contents of the program counter are the skipped address. (4) The contents of the window register (WR), bank register (BANK), general register pointer (RP), and program status word (PSWORD) are saved to the interrupt stack. (5) The contents of the vector address generator corresponding to the accepted interrupt are transferred to the program counter. The result is that execution branches to an interrupt processing routine. Processing (1) through (5) above is executed in one special instruction cycle (4.44 s) not accompanied by normal instruction execution. This instruction cycle is called an "interrupt cycle". Therefore, one instruction cycle time is required after an interrupt has been accepted until execution branches to the corresponding vector address.
10.8 Returning from Interrupt Processing Routine
To return execution from an interrupt processing routine to the processing during which the interrupt was accepted, a dedicated instruction, "RETI", is used. When this instruction is executed, the following processing is sequentially executed automatically: (1) The contents of the address stack register specified by the stack pointer are restored to the program counter. (2) The contents of the interrupt stack are restored to the window register (WR), bank register (BANK), general register pointer (RP), and program status word (PSWORD). (3) The contents of the stack pointer are incremented by one. Processing (1) through (3) above is performed in one instruction cycle in which the "RETI" instruction is executed. The difference between the "RETI" instruction and the subroutine return instructions "RET" and "RETSK" is how the contents of the window register, bank register, general register pointer, and program status word are restored, as in step (2) above.
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10.9 External (INT0 and INT1 Pins) Interrupts
10.9.1 Outline of external interrupt Figure 10-5 outlines external interrupts. As shown in this figure, an external interrupt request is issued when a rising edge or falling edge is input to the INT0 or INT1 pin. Whether the interrupt request is issued at the rising or falling edge is set independently by program. The INT0 and INT1 pins are Schmit trigger input pins to prevent malfunctioning due to noise. These pins do not accept a pulse input of less than 1 s. Figure 10-5. Outline of External Interrupts
INT0 flag Detects pin status
IEG0 flag Interrupt control block Sets interrupt edge Edge detection
INT0 pin
IRQ0 flag
Schmitt trigger
INT1 flag Detects pin status
IEG1 flag Sets interrupt edge Edge detection
INT1 pin
IRQGRP flag
Schmitt trigger
10.9.2 Edge detection block The edge detection block sets the input signal edge (rising or falling) at which interrupt requests are issued from the INT0 and INT1 pins, and detects the set edge. The edge is set by the IEG0 and IEG1 flags. The configuration and function of each flag are described next.
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Flag Symbol Name b3 Interrupt edge select register (INTEDGE) b2 b1 I E G 1 b0 I E G 0 Address
Read/ Write
0
0
1FH
R/W
Sets input edge at which interrupt request of INT0 pin is issued 0 1 Rising edge Falling edge
Sets input edge at which interrupt request of INT1 pin is issued 0 1 Rising edge Falling edge
Fixed to "0"
On reset
Power-ON Clock stop CE
0
0
0 0 0
0 0 0
When the edge at which the interrupt request is issued is changed by the IEG0 and IEG1 flags, the interrupt request signal may be issued as soon as the edge has been changed. For example, suppose, as shown in Table 10-2, that the IEG0 flag is now set to "1" (specifying the falling edge) and that a high level is input from the INT0 pin. If the IEG0 flag is reset at this time, the edge detection circuit assumes that the rising edge has been input, and issues the interrupt request. Table 10-2. Issuance of Interrupt Request by Changing IEG0 and IEG1 Flags
Changes in IEG0 and IEG1 Flags 10 (falling) (rising) Status of INT0 and INT1 Pins Low level High level Low level High level Issuance of Interrupt Request Not issued Issued Issued Not issued Status of IRQ0 and IRQGRP Flags Retains previous status Set to "1" Set to "1" Retains previous status
01 (rising) (falling)
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10.9.3 Pin status detection block The level of the signals input to the INT0 and INT1 pins can be detected by using the INT0 and INT1 flags. The INT0 and INT1 flags can be set to "1" or reset to "0" via window register, regardless of whether an interrupt request is issued or not. Therefore, these pins can be used as a 2-bit general-purpose input port when the interrupt function is not used. If interrupts are not enabled, these flags can be used as a general-purpose input port that can detect the rising edge or falling edge by reading the contents of the corresponding interrupt request flags (IRQ0 and IRQGRP flags). In this case, however, the interrupt request flags are not automatically reset to "0" and must be reset by program. For the details of the configuration and function of the INT0 and INT1 flags, refer to 10.2 Interrupt Control Block.
10.10 Internal Interrupts
Five internal interrupt sources are available: timer/counter overflow, 12-bit timer, basic timer 1, serial interface 0, and frequency counter. 10.10.1 Timer/counter overflow interrupt The timer/counter overflow interrupt issues an interrupt request when the 12-bit timer/counter overflows. The timer/counter overflow interrupt or the interrupt caused by the INT1 pin can be selected by using the IGRPSL flag. The configuration and function of this flag are shown below. For details, refer to 10.9 External (INT0 and INT1 Pins) Interrupts and 11. TIMER FUNCTION.
Flag Symbol Name b3 b2 b1 b0 I G R P S L Address
Read/ Write
Group interrupt select register (IGRPSELR)
0
0
0
0FH
R/W
Sets interrupt source of IRQGRP flag 0 1 Issues interrupt request by INT1 pin Issues interrupt request by overflow of timer/counter
Fixed to "0"
On reset
Power-ON Clock stop CE
0
0
0
0 0 0
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10.10.2 12-bit timer interrupt The 12-bit timer interrupt request can be issued at fixed time intervals. For details, refer to 11. TIMER FUNCTION. 10.10.3 Basic timer 1 interrupt The basic timer 1 interrupt request can be issued at fixed time intervals. For details, refer to 11. TIMER FUNCTION. 10.10.4 Serial interface 0 interrupt The serial interface 0 interrupt request can be issued at completion of the serial out or serial in operation. For details, refer to 19. SERIAL INTERFACE. 10.10.5 Frequency counter The frequency counter interrupt request can be issued at completion of the count operation. For details, refer to 20. FREQUENCY COUNTER (FC).
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11. TIMER FUNCTION
The timer function is used to control program execution time.
11.1 Configuration of Timer
Figure 11-1 shows the configuration of the timer. As shown in this figure, the timer block consists of a basic timer 0 carry block, basic timer 1 interrupt block, and 12-bit timer block. The clock generation circuit that sets time to each timer consists of a clock select blocks A, B, and C, basic timer clock select register (BTMCLK: RF address 09H) of the control register, and timer counter clock select register (TMCLK: RF address 0CH). The clock of each timer is generated by dividing the system clock (4.5 MHz). If the crystal oscillator is not 4.5 MHz, the clock of each timer changes accordingly. 11.1.1 Configuration of basic timer 0 carry block The basic timer 0 carry block consists of a clock select block A and basic timer 0 carry FF block. 11.1.2 Configuration of basic timer 1 interrupt block The basic timer 1 interrupt block consists of a clock select block B and interrupt control block. 11.1.3 Configuration of 12-bit timer block The 12-bit timer block consists of a clock select block C, 12-bit timer mode control block, count block, and interrupt control block.
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Figure 11-1. Configuration of Timer Block * Basic timer 0 carry block
Control register
4.5 MHz
Clock select A
Basic timer 0 carry FF
* Basic timer 1 interrupt block
Control register
4.5 MHz
Clock select B
Interrupt control
Interrupt request signal
* 12-bit timer block
Control register
4.5 MHz
Clock select C
12-bit timer mode control
Overflow detection Count block
Interrupt control
Interrupt request signal
Data buffer
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11.2 Functional Outline of Timer
The timer can be used in three ways: to detect the carry FF of the basic timer 0 carry, to use the interrupt of basic timer 1, and to use the interrupt of the 12-bit timer. 11.2.1 Functional outline of basic timer 0 carry The basic timer 0 carry controls time by detecting via program the status of the basic timer 0 carry FF that is set at fixed intervals. For details, refer to 11.3 Basic Timer 0 Carry. 11.2.2 Functional outline of basic timer 1 interrupt The basic timer 1 interrupt controls time by generating an interrupt at fixed time intervals. For details, refer to 11.4 Basic Timer 1 Interrupt. 11.2.3 Functional outline of 12-bit timer The 12-bit timer counts up the basic clocks with a 12-bit counter. When the count value coincides with the data set by program, it generates an interrupt to control time. For details, refer to 11.5 12-Bit Timer.
11.3 Basic Timer 0 Carry
11.3.1 Configuration of basic timer 0 carry Figure 11-2 shows the configuration of the basic timer 0 carry. As shown in this figure, the basic timer 0 carry consists of a divider, selector, and basic timer 0 carry FF block. Figure 11-2. Configuration of Basic Timer 0 Carry
Control Register Basic Timer Clock Select Name (BTMCLK) Address Bit b3 B T M 1 C K 1 b2 B T M 1 C K 0 09H b1 B T M 0 C K 1 b0 B T M 0 C K 0 b3 b2 Basic Timer 0 Carry FF Judge (BTM0CYJG) 17H b1 b0 B T M 0 C Y
Flag symbol
0
0
0
Selector 250 ms 4.5 MHz Divider 100 ms 5 ms 1 ms Basic timer 0 carry FF
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11.3.2 Function of basic timer 0 carry The basic timer 0 carry is set to 1 at the rising edge of the basic timer 0 carry FF setting pulse set by the lower 2 bits (BTM0CK1 and BTM0CK0 flags) of the basic timer clock select register. The content of the basic timer 0 carry FF corresponds to the least significant bit (BTM0CY flag) of the basic timer 0 carry FF judge register (BTM0CYJG: RF address 17H) on a one-to-one basis. When the basic timer 0 carry FF is set to 1, the BTM0CY flag is simultaneously set to 1. The BTM0CY flag is reset to 0 on reading its content to the window register by the "PEEK"instruction (Read & Reset). When the BTM0CY flag is reset to 0, the basic timer 0 carry FF is simultaneously reset to 0. By reading the BTM0CY flag by program, therefore, a timer with the time set via the basic timer clock select register can be created. When using the basic timer 0 carry, bear in mind the following point: Caution The basic timer 0 carry is disabled from being set on power application (at VDD reset) and is not set until the content of the BTM0CY flag is once read by the "PEEK" instruction. Consequently, when the BTM0CY flag is read for the first time after power-ON reset, "0" is always read. After that, the flag is set to 1 at time intervals set by the basic timer clock select register. The basic timer 0 carry also controls the timing of reset by the CE pin (CE reset). When the CE pin goes high, CE reset is effected in synchronization with the timing at which the basic timer 0 carry FF is set next. Therefore, a power failure can be detected by reading the content of the BTM0CY flag at system reset (powerON reset or CE reset). For details, refer to 11.3.7 Notes on using basic timer 0 carry and 13. RESET. Because the BTM0CY flag is a read-only flag, the device operation is not affected in any way even if data is written to this flag by using the "POKE" instruction. However, an error occurs when the 17K series assembler (AS17K) is used. For details, refer to 8.4 Notes on Using Register File.
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11.3.3 Configuration and function of basic timer clock select register (BTMCLK) The basic timer clock select register sets two time intervals of the internal basic timer 0 carry and basic timer 1 interrupt. The time intervals of the basic timer 0 carry and basic timer 1 interrupt can be independently set. The configuration and function are shown next. Figure 11-3 shows the waveform of the timer time setting pulse.
Flag Symbol Name b3 B T M 1 C K 1 b2 B T M 1 C K 0 b1 B T M 0 C K 1 b0 B T M 0 C K 0 Address
Read/ Write
Basic timer clock select register (BTMCLK)
09H
R/W
Sets time interval at which basic timer 0 carry is set 0 0 1 1 0 1 0 1 100 ms 250 ms 5 ms 1 ms
Sets time interval at which basic timer 1 interrupt is setNote 0 0 1 1 0 1 0 1 100 ms 250 ms 5 ms 1 ms
On reset
Power-ON Clock stop CE
0 0
0 0
0 0
0 0
Retained
Note
Refer to 11.4 for the basic timer 1 interrupt.
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Figure 11-3. Waveform of Timer Time Setting Pulse
1 kHz 0.33 ms 1 ms 0.67 ms
200 Hz 2 ms 5 ms 3 ms
10 Hz 50 ms 100 ms 50 ms
4 Hz 100 ms 250 ms 150 ms
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11.3.4 Configuration and function of basic timer 0 carry flip-flop (FF) judge register (BTM0CYJG) The basic timer 0 carry flip-flop (FF) judge register detects the status of the basic timer 0 carry flip-flop (FF) of the internal timer. The configuration and function of BTM0CYJG are illustrated below.
Flag Symbol Name b3 b2 b1 b0 B T M 0 C Y Address
Read/ Write
Basic timer 0 carry FF judge register (BTM0CYJG)
0
0
0
17H
R & Reset
Detects status of basic timer 0 carry FF 0 1 Basic timer 0 carry FF is not set Basic timer 0 carry FF is set
Fixed to "0"
On reset
Power-ON Clock stop CE
0
0
0
0 1 1
The BTM0CY flag is set at time intervals set by the basic timer clock select register (BTMCLK). The status of this flag is detected by the "PEEK" instruction via the window register. If the BTM0CY flag is set at this time, its value is transferred to the window register and then the BTM0CY flag is reset (Read & Reset). Because the BTM0CY flag is reset to "0" at power-ON reset and is set to "1" at CE reset and at CE reset after execution of the clock stop instruction, it can be used to detect a power failure. The BTM0CY flag is not set once VDD has been applied until the "PEEK" instruction is executed. Once the "PEEK" instruction has been executed, it is set at time intervals set by the basic timer clock select register.
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11.3.5 Example of use of timer with BTM0CY flag Here is a program example: Example M1 MEM 0.10H ; 1-second counter ; Embedded macro ; Sets basic timer 0 carry FF setting time to 250 ms LOOP: SKT1 BR ADD SKT1 BR NEXT: Processing B BR LOOP ; Executes processing B and branches to LOOP BTM0CY NEXT M1, #0100B CY NEXT Processing A ; Adds 4 to data memory M1 ; Embedded macro ; Tests CY flag ; If it is "0", branches to NEXT ; If it is "1", executes processing A ; Embedded macro ; Tests BTM0CY flag. If it is "0", branches to NEXT INITFLG NOT BTM0CK1, BTM0CK0
This program executes processing A every 1 second. When creating this program, the following point must be noted. Caution The time interval at which the BTM0CY flag is detected must be shorter than the time interval at which the basic timer 0 carry FF is set to 1. In the above example, if processing B requires 250 ms or longer as shown in Figure 11-4, the basic timer 0 carry FF is not set. Figure 11-4. Detection of BTM0CY Flag and Basic Timer 0 Carry FF
Basic timer 0 carry FF setting pulse
H L 1 <1> <2> <3> <4> <5>
BTM0CY flag 0 SKT 1 BTM0CY SKT 1 BTM0CY Processing B' SKT 1 BTM0CY
Processing B
Status of BTM0CY flag set in <3> is not detected because time of processing B' is too long after BTM0CY flag that was set in <2> has been detected.
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11.3.6 Timer error due to BTM0CY flag Timer errors due to the BTM0CY flag include an error due to the detection time of the BTM0CY flag and an error that occurs when the basic timer 0 carry FF setting time is changed. The following paragraphs (1) and (2) describe the respective errors. (1) Error due to detection time of BTM0CY flag As described in 11.3.5, the time interval at which the BTM0CY flag is detected must be shorter than the time interval at which the basic timer 0 carry FF is set to 1. Where the time interval at which the BTM0CY flag is detected is tCHECK and the time interval at which the basic timer 0 carry FF is set is tSET (250 ms, 100 ms, 5 ms, or 1 ms), the relation between the two must be as follows: tCHECK < tSET The timer error when the BTM0CY flag is detected is as shown in Figure 11-5. 0 < error < tCHECK Figure 11-5. Error due to BTM0CY Flag Detection Time Interval
H L 1 BTM0CY flag 0 tCHECK 1 SKT 1 BTM0CY <1> tCHECK 2 SKT 1 BTM0CY <2> tCHECK 3 SKT 1 BTM0CY <4> tSET
Basic timer 0 carry FF setting pulse
SKT 1 BTM0CY <3>
As shown in Figure 11-5, when the BTM0CY flag is detected in <2>, the timer is updated because the flag is "1". When the BTM0CY flag is detected next time in <3>, the timer is not updated until the flag is detected again in <4> because the flag is "0". Consequently, the time of the timer at this time is extended by the time of tCHECK3.
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(2) Error when basic timer 0 carry FF setting time is changed The basic timer 0 carry FF setting time is set by the BTM0CK1 and BTM0CK0 flags of the basic timer clock select register. As shown in Figures 11-2 and 11-3, the timer time setting pulse can be selected from the four types: 1 kHz, 200 Hz, 10 Hz, and 4 Hz. These four types of pulses operate independently of each other. Therefore, if the timer time setting pulse is changed by the BTM0CK1 and BTM0CK0 flags, an error occurs as shown in the example below. Example ; <1> INITFLG BTM0CK1, NOT BTM0CK0 ; Embedded macro ; Sets basic timer 0 carry FF setting pulse to 200 Hz (5 ms) Processing A ; <2> SET2 BTM0CK1, BTM0CK0 ; Embedded macro ; Sets basic timer 0 carry FF setting pulse to 1 kHz (1 ms) Processing A ; <3> INITFLG BTM0CK1, NOT BTM0CK0 ; Embedded macro ; Sets the basic timer 0 carry FF setting pulse to 200 Hz (5 ms) At this time, the basic timer 0 carry FF setting pulse is changed as follows:
H L H L H L <1> 1 BTM0CY flag 0 SKT1 BTM0CY Instruction of <2> Instruction of <3>
Internal pulse 200 Hz Internal pulse 1 kHz Basic timer 0 carry FF setting pulse
As shown above, by changing the setting time of the basic timer 0 carry FF, the BTM0CY flag holds the previous status when the new pulse falls (<2> in the above figure). If the pulse rises, however, the BTM0CY flag is set to 1 (<3> in the figure).
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In the above example, the pulse frequency is changed between 200 Hz (5 ms) and 1 kHz (1 ms). The same applies to change between 4 Hz (250 ms) and 10 Hz (100 ms). Therefore, as shown in Figure 11-6, the error that may occur until the BTM0CY flag is set first after the basic timer 0 carry FF setting time has been changed is as follows: -tSET < error < tCHECK where, tSET : new basic timer 0 carry FF setting time tCHECK : time required to detect BTM0CY flag A phase difference is provided among the internal pulses of 4 Hz, 10 Hz, 200 Hz, and 1 kHz. Because this phase difference is shorter than the new pulse time, it is included in the above error. For the phase difference of each pulse, refer to 11.4.5 Notes on using basic timer 1 interrupt. Figure 11-6. Errors When Basic Timer 0 Carry FF Setting Time Is Changed from A to B
<1> Error of -tSET Internal pulse A Internal pulse B Basic timer 0 carry FF setting pulse H L H L H L 1 BTM0CY flag 0 SKT1 BTM0CY ~0 tSET
<2> Error of tCHECK
tSET
~0
tCHECK
Original timer time Actual timer time Time changed -tSET error occurs if BTM0CY flag is detected immediately after timer time has been changed because the flag is "1".
Original timer time Actual timer time Time changed Error of tCHECK occurs because BTM0CY flag is reset once if timer time is changed immediately after BTM0CY flag has been detected.
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11.3.7 Notes on using basic timer 0 carry The basic timer 0 carry is used not only as a timer but also as a reset synchronization signal when reset is effected by using the CE pin (CE reset). If the next basic timer 0 carry FF setting pulse rises after the CE pin has gone high, CE reset is effected. At this time, the following points must be noted. (1) The sum of the timer updating processing time and the BTM0CY flag detection time interval must be shorter than the basic timer 0 carry FF setting time. (2) When a program in which the timer always operates after power application (power-ON reset) regardless of CE reset is created, the timer must be adjusted each time the CE reset is effected. (3) Detection of the BTM0CY flag takes precedence over the reset synchronization signal at CE reset. Therefore, if the two contend, CE reset is delayed once. Above (1) through (3) are described in (a) through (c) below.
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(a) Timer updating processing time and BTM0CY flag detection time interval As described in 11.3.6, the time interval tSET at which the BTM0CY flag is detected must be shorter than the time interval at which the basic timer 0 carry FF is set. Even if the time interval at which the BTM0CY flag is detected is short, if the timer updating processing time is long, the timer processing may not be correctly performed if CE reset is effected. Therefore, the following condition must be satisfied: tCHECK + tTIMER < tSET where, tCHECK : time interval at which BTM0CY flag is detected tTIMER : timer updating processing time tSET Here is an example: Example Example of timer updating processing and BTM0CY flag detection time interval START : ; Program address 0000H ; Embedded macro ; Sets basic timer 0 carry FF setting time to 100 ms BTIMER : ; <1> SKT1 BTM0CY BR BR AAA : Processing A BR BTIMER AAA BTIMER ; Embedded macro ; Tests BTM0CY flag. ; If it is "0", branches to AAA. Timer updating : time interval at which basic timer 0 carry FF is set
CLR2 BTM0CK1, BTM0CK0
Here is the timing chart of the above program:
H CE pin Basic timer 0 carry FF setting pulse BTM0CY flag 0 BTM0CY detection interval tCHECK SKT 1 BTM0CY SKT 1 BTM0CY CE reset Timer updating processing tTIMER If this processing time is too long, CE reset is effected during processing. L H L 1
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(b) Adjusting basic timer 0 carry on CE reset An example of adjusting the timer at CE reset is given below. As shown in this example, the timer must be adjusted at CE reset "when the basic timer 0 carry FF is used for power failure detection and the basic timer 0 carry FF is used as a watch timer". The basic timer 0 carry FF is reset to 0 on the first power application (power-ON reset) and is disabled from being set until the BTM0CY flag is once read by using the "PEEK" instruction. When the CE pin goes high, CE reset is effected in synchronization with the rising edge of the basic timer 0 carry FF setting pulse. At this time, the BTM0CY flag is set to 1 and the timer operation is started. Therefore, by detecting the status of the BTM0CY flag on system reset (power-ON reset or CE reset), whether power-ON reset or CE reset has been effected can be judged (The BTM0CY flag is "0" when power-ON reset has been effected. It is "1" when CE reset has been effected) (power failure detection). At this time a watch timer should continue its operation even at CE reset. However, when the BTM0CY flag has been read to detect a power failure, the flag is reset to 0. Consequently, the set (1) status of the flag is overlooked once. For this reason, the watch timer must be updated if CE reset has been detected as a result of power failure detection. For further information on power failure detection, also refer to 13.6 Power Failure Detection.
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Example Adjusting timer on CE reset To detect power failure and update watch by using basic timer 0 carry START : Processing A ; <1> SKT1 BR BACKUP : ; <2> Updates 100-ms watch LOOP : ; <3> Processing B SKF1 BR BR INITIAL : CLR2 BTM0CK1, BTM0CK0 ; Embedded macro ; Because power failure (power-ON reset) occurs, ; sets basic timer 0 carry FF setting time to 100 ms, ; and executes processing C. Processing C BR LOOP BTM0CY BACKUP LOOP ; Updates watch by testing BTM0CY flag, ; while executing processing B ; Adjusts timer because backup (CE reset) has been effected BTM0CY INITIAL ; Embedded macro ; Tests BTM0CY flag If it is "0", branches to INITIAL (power failure detection) ; Program address 0000H
Figure 11-7 is a timing chart illustrating the above program.
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Figure 11-7. Timing Chart
VDD CE Internal pulse 10 Hz Basic timer 0 carry FF setting pulse BTM0CY flag Program processing Program instruction 5V 0V H L H L H L 1 0
A <1> C <3> B <3> Watch UP B <3> B <3> B B <3><3> B B <3><3> Watch UP B B B A <1> B B <3><3> Watch UP B
<3><3> Watch UP
Watch UP
Power Power-ON reset application Starts from address 0 BTM0CY flag detection
CE reset Starts from address 0 Time updated because BTM0CY flag is set (1)
Point A
Point B
Point C
Point D
Point E
As shown in this figure, the program is started from address 0000H at the rising edge of the internal 10-Hz pulse on application of supply voltage VDD at first. When the BTM0CY flag is detected next at point A, a power failure (power-ON reset) is detected because the BTM0CY flag is reset to 0 on power application. Therefore, "processing C" is executed and the basic timer 0 carry FF setting pulse is set to 100 ms. Because the contents of the BTM0CY flag have been read once at point A, the BTM0CY flag is set to 1 every 100 ms. If the CE pin goes low at point B and then high at point C, the program counts up the watch while executing "processing B", unless the clock stop instruction is executed. Because the CE pin goes high at point C, CE reset is effected at point D where the next basic timer 0 carry FF setting pulse rises. Consequently, the program starts from address 0000H. If the BTM0CY flag is detected at point E at this time, backup (CE reset) is assumed because the flag is set to 1. As is evident from the figure, unless the watch is updated by 100 ms at point E, the watch is delayed by 100 ms each time CE reset is effected. If processing A takes 100 ms or longer when a power failure is detected at point E, setting of the BTM0CY flag is overlooked two times. Therefore, processing A must be executed shorter than 100 ms. The above description also applies when 250 ms, 5 ms, or 1 ms is selected as the basic timer 0 carry FF setting pulse. Therefore, the BTM0CY flag must be detected in order to detect a power failure less than the basic timer 0 carry FF setting time after the program has been started from address 0000H.
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(c) If detection of BTM0CY flag collides with CE reset As described in (b), CE reset is effected as soon as the BTM0CY flag is set to 1. At this time if an instruction that reads the BTM0CY flag happens to be executed at the same time as CE reset, the BTM0CY flag read instruction takes precedence. Therefore, if setting of the BTM0CY flag (rising of the basic timer 0 carry FF setting pulse) after the CE pin has gone high collides with the BTM0CY flag read instruction, CE reset is effected "when the BTM0CY flag is set next time". This operation is illustrated in Figure 11-8. Figure 11-8. Operation If CE Reset Collides with BTM0CY Flag Read Instruction
H L H L 1 0 SKT 1 BTM0CY Basic timer 0 carry FF setting pulse BTM0CY flag Instruction H L 1 0
SKT1 BTM0CY (PEEK...) (SKT...)
CE pin Basic timer 0 carry FF setting pulse BTM0CY flag
SKT 1 BTM0CY
CE reset
Embedded macro PEEK WR, .MF BTM0CY SHR 4 SKT WR, # .DF. BTM0CY AND 000 FH 4.44 s If BTM0CY flag is read during this period, CE reset is delayed once. Normally program is started from address 0000H here. However, CE reset is not effected because program that reads BTM0CY happens to be executed.
Therefore, if the program that cyclically detects the BTM0CY flag and in which the detection time interval of the BTM0CY flag coincides with the BTM0CY flag setting time, CE reset is never effected. Remember the following point: Because one instruction cycle is 4.44 s (1/225 kHz), a program, for example, that detects the BTM0CY flag once each time 255 instructions have been executed reads the BTM0CY flag every 1 ms (= 4.44
s x 225).
At this time, once setting and detection of the BTM0CY flag have coincided, CE reset is never effected, regardless of whether the 1-, 5-, 100-, or 250-ms timer time setting pulse is selected. Therefore, do not create a program with a cycle that satisfies the following condition: tSETx225 = n (n: natural number) X where, tSET: BTM0CY flag setting time X : step X of instruction in which BTM0CY flag is read
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Here is an example of a program that satisfies the above condition. Do not create such a program. Example Processing A SET2 BTM0CK1, BTM0CK0 ; Embedded macro ; Sets basic timer 0 carry FF setting pulse to 1 ms LOOP : ;<1> SKT1 BTM0CY BR AAA : 221 steps BR BBB : 221 steps BR LOOP LOOP BBB ; Embedded macro
In this example, the BTM0CY flag read instruction in <1> is repeated each time 225 instructions have been executed. If the BTM0CY flag happens to be set when instruction <1> is executed, CE reset is not effected after that.
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11.4 Basic Timer 1 Interrupt
11.4.1 Configuration of basic timer 1 interrupt block Figure 11-9 shows the configuration of the basic timer 1 interrupt block. As shown in this figure, the basic timer 1 interrupt block consists of a divider, a selector, and an interrupt control block. Figure 11-9. Configuration of Basic Timer 1 Interrupt Block
Control Register
Name
Basic Timer Clock Select (BTMCLK)
Basic Timer 1 Interrupt Request (lREQBTM1)
Interrupt Permission 2 (lNTPM2)
Address Bit b3 B T M 1 C K 1
09H b2 B T M 1 C K 0 b1 B T M 0 C K 1 b0 B T M 0 C K 0 b3
3CH b2 b1 b0 I R Q B T M 1 b3 I P B T M 1
2FH b2 I P T M b1 I P G R P b0 I P 0
Flag symbol
0
0
0
Selector 250 ms 4.5 MHz Divider 100 ms 5 ms 1 ms Interrupt control block Issues interrupt request
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11.4.2 Function of basic timer 1 interrupt block The basic timer 1 interrupt block issues an interrupt request at the falling edge of the basic timer 1 interrupt pulse set by the higher 2 bits (BTM1CK1 and BTM1CK0 flags) of the basic timer clock select register. The basic timer 1 interrupt request corresponds to the IRQBTM1 flag of the basic timer 1 interrupt request register (IREQBTM1: RF address 3CH) on a one-to-one basis, and the IRQBTM1 flag is set to 1 when the basic timer 1 interrupt request is issued. When the basic timer 1 interrupt pulse falls, therefore, the IRQBTM1 flag is set to 1. So that the basic timer 1 interrupt may occur, the interrupt request must be issued, the "EI" instruction which enables all the interrupts must be issued, and the basic timer 1 interrupt must be enabled, as described in 10. INTERRUPT. To enable the basic timer 1 interrupt, set the IPBTM1 flag of the interrupt permission 2 register (INTPM2: RF address 2FH) to 1. Therefore, the basic timer 1 interrupt is accepted if the IRQBTM1 flag is set to 1 when the "EI" instruction has been executed and the IPBTM1 flag has been set to 1. When the basic timer 1 interrupt has been accepted, the program flow is transferred to program memory address 0003H. The IRQBTM1 flag is reset to 0 when the interrupt has been accepted. Figure 11-10 shows the relation between the basic timer 1 interrupt pulse and IRQBTM1 flag. Figure 11-10. Relation between Basic Timer 1 Interrupt Pulse and IRQBTM1 Flag
Basic timer 1 interrupt pulse IRQBTM1 IPBTM1 INTE FF H L 1 0 1 0 EI DI
<1> Interrupt accepted
IRQBTM1 flag is set at falling edge of basic timer 1 interrupt pulse
Interrupt is not accepted even if EI instruction is executed because IPBTM1 flag is not set Interrupt enable period
Timer interrupt is accepted as soon as IPBTM1 flag is set
Interrupt pending period
The point that must be remembered here is that the basic timer 1 interrupt is accepted when the "EI" instruction is executed and the IPBTM1 flag is set, as shown in <1> in Figure 11-10, once the IRQBTM1 flag is set when the timer interrupt is disabled by the "DI" instruction or IPBTM1 flag. In this case, the interrupt request is cleared if "0" is written to the IRQBTM1 flag. If "1" is written to the IRQBTM1 flag, the operation is equivalent to issuance of the interrupt request. When the basic timer 1 interrupt is accepted, one level of the stack is used. The contents of the window register (WR), bank register (BANK), general register pointer (RP), and program status word (PSWORD) are automatically saved. To return from the interrupt processing routine, use the dedicated instruction "RETI". For details, refer to 3. ADDRESS STACK (ASK) and 10. INTERRUPT.
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For the configuration and function of the basic timer clock select register, refer to 11.3.3. 11.4.3 and 11.4.4 below describe an example of using the basic timer 1 interrupt and an error of the basic timer 1 interrupt. For the relation between the basic timer 1 interrupt and other interrupts (such as INT0 pin, INT1 pin, 12-bit timer, serial interface 0, and frequency counter interrupts), refer to 10. INTERRUPT. 11.4.3 Example of timer using basic timer 1 interrupt Example M1 BTIMER1 MEM DAT BR ORG BTIMER1 ADD SKT1 BR EI_RETI: EI RETI START: INITFLG BTM1CK1, NOT BTM1CK0 ; Embedded macro ; Sets basic timer 1 interrupt pulse to 5 ms MOV SET1 EI LOOP: Processing B BR LOOP This program executes processing A every 80 ms. The points to be noted in this case are that the DI status is automatically set when the interrupt has been accepted, and that the IRQBTM1 flag is set to 1 even in the DI status. If processing A takes 5 ms or longer, therefore, the interrupt is accepted as soon as execution is returned by the "RETI" instruction, and as a result, processing B is not executed. M1, #0000B IPBTM1 ; Clears contents of M1 to 0 ; Enables basic timer 1 interrupt ; Enables all interrupts M1, #0001B CY EI_RETI Processing A 0.10H 0003H START ; 80-ms counter ; Defines symbol of basic timer interrupt vector address ; Branches to START ; Program address (0003H) ; Adds 1 to M1 ; Tests CY flag ; Returns if carry does not occur
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11.4.4 Error of basic timer 1 interrupt As described in 11.4.2, the interrupt is accepted each time the basic timer 1 interrupt pulse falls if the EI instruction has been executed and the basic timer 1 interrupt has been enabled. Therefore, a timer error only occurs when the basic timer 1 interrupt is used in the following cases: (1) When the first interrupt is accepted after the basic timer 1 interrupt has been enabled (2) When the first interrupt is accepted after the time of the basic timer 1 interrupt pulse is changed (3) When the IRQBTM1 flag is written Figure 11-11 shows an error that may occur in each of the above cases. Figure 11-11. Error of Basic Timer 1 Interrupt (1/2) (a) When basic timer 1 interrupt is enabled
Basic timer 1 interrupt pulse IRQBTM1 IPBTM1 INTE FF H L 1 0 1 0 EI DI
tSET
EI
Interrupt pending
EI EI <3> Interrupt accepted Interrupt accepted <1><2> SET1 IPBTM1 Interrupt accepted
When basic timer 1 interrupt is enabled by setting the IPBTM1 flag in point <1> above, the interrupt is immediately accepted. The error at this time is -tSET. If the interrupt is subsequently enabled by the "EI" instruction at point <2>, the interrupt occurs at the falling edge of the basic timer 1 interrupt pulse at point <3>. At this time, the relation between -tSET and error is as follows: -tSET < error < 0
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Figure 11-11. Error of Basic Timer 1 Interrupt (2/2) (b) When basic timer 1 interrupt pulse is changed
Internal pulse A Internal pulse B Basic timer 1 interrupt pulse IRQBTM1 IPBTM1 INTE FF H L H L H L 1 0 1 0 EI DI <1> Basic timer 1 interrupt pulse changed Interrupt accepted EI <3> Basic timer 1 interrupt pulse changed
EI
EI
EI Interrupt accepted
<2> Interrupt accepted
Because the basic timer 1 interrupt pulse does not fall even if basic timer 1 interrupt pulse is changed to B in <1>, the interrupt is accepted in <2>. Because the basic timer 1 interrupt pulse falls if the basic timer 1 interrupt pulse is changed to A in <3>, the interrupt is immediately accepted. (c) When IRQBTM1 flag is manipulated
Basic timer 1 interrupt pulse IRQBTM1 IPBTM1 INTE FF H L 1 0 1 0 EI DI EI Interrupt accepted EI <1> SET1 IRQBTM1 <2> CLR1 IRQBTM1 Interrupt accepted Interrupt not accepted EI Interrupt accepted
If the IRQBTM1 flag is set in <1>, the interrupt is immediately accepted. If resetting the IRQBTM1 flag collides with the falling of the basic timer 1 interrupt pulse in <2>, the interrupt is not accepted.
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11.4.5 Notes on using basic timer 1 interrupt When creating a program, in which the basic timer 1 always operates for a specific time after once power has been applied (power-ON reset) such as a watch program, using the basic timer 1 interrupt the basic timer 1 interrupt processing time must be completed in a specific time. This is described by taking the following example. Example M1 BTIMER1 MEM DAT BR ORG BTIMER1 ADD SKT1 BR ; <1> Watch processing EI_RETI: EI RETI START: INITFLG NOT BTM1CK1, BTM1CK0, NOT BTM0CK1, NOT BTM0CK0 ; Embedded macro ; Sets basic timer 1 interrupt time to 250 ms and basic timer 0 carry ; FF setting time to 100 ms SET1 EI LOOP: Processing A BR LOOP IPBTM1 ; Embedded macro ; Enables basic timer 1 interrupt ; Enables all interrupts M1, #0100B CY EI_RETI 0.10H 0003H START ; 1-ms counter ; Symbol definition of basic timer interrupt vector address ; Branches to START ; Program address (0003H) ; Adds 0100B to M1 ; Watch processing if carry occurs ; Returns if carry does not occur
In this example, watch processing <1> is executed every 1 second while processing A is executed. If the CE pin goes high as shown in Figure 11-12 (a), CE reset is effected in synchronization with the rising of the basic timer 0 carry FF setting pulse. If the basic timer 1 interrupt request is issued at the same time as the setting of the basic timer 0 carry FF, CE reset takes precedence. When CE reset is effected, the basic timer 1 interrupt request (IRQBTM1 flag) is reset. Consequently, timer processing is not performed once.
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To prevent this, actually there is a delay between the "rising of the basic timer 0 carry FF setting pulse" and "falling of the basic timer 1 interrupt pulse", as shown in Figure 11-12 (b). Therefore, as shown in Figure 11-12 (b), the basic timer 1 interrupt occurs without fail even if CE reset is effected, if the watch processing is performed within 10 ms. Because four types of basic timer 0 carry FF and basic timer 1 interrupt time setting pulses, 4 Hz (250ms), 10 Hz (100 ms), 200 Hz (5 ms), and 1 kHz (1 ms), can be set separately, a time difference is provided as shown in Figure 11-13 and Table 11-1. If it is necessary to enable the basic timer 1 interrupt even at CE reset, the basic timer 1 interrupt processing must be completed within the delay time of the pulse as shown in Figure 11-13. Figure 11-12. Timing Chart (a)
CE pin Basic timer 0 carry FF setting pulse Basic timer 1 interrupt pulse H L H L H L Basic timer 1 interrupt Because basic timer 0 carry FF setting pulse rises, CE reset is effected here, and basic timer 1 interrupt is missed once.
(b)
CE pin Basic timer 0 carry FF setting pulse Basic timer 1 interrupt pulse H L H L H L Delay time (10 ms in this case) Basic timer 1 interrupt Basic timer 1 interrupt CE reset Because there is a delay of 10 ms between the falling of the basic timer 1 interrupt pulse and the rising of the basic timer 0 carry FF setting pulse, if the basic timer 1 interrupt processing is performed within 10 ms, the timer processing is normally executed even if CE reset is effected.
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Figure 11-13. Time Difference between Basic Timer 0 Carry FF Setting Pulse and Basic Timer 1 Interrupt Pulse
1 ms BTM0CY 2:1:1 1 ms INT 1 ms
5 ms BTM0CY 5 ms INT
Dummy 10 ms 100 ms BTM0CY 100 ms INT 250 ms BTM0CY 250 ms INT
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Table 11-1. Time Difference between Rising Edge of Basic Timer 0 Carry FF Pulse and Falling Edge of Basic Timer 1 Interrupt Pulse Internal Pulse Minimum Value of Time Difference (See Figure below) Basic Timer 0 Carry Basic Timer 1 Interrupt 1 ms 1 ms 1 ms 1 ms 5 ms 5 ms 5 ms 5 ms 100 ms 100 ms 100 ms 100 ms 250 ms 250 ms 250 ms 250 ms 1 ms 5 ms 100 ms 250 ms 1 ms 5 ms 100 ms 250 ms 1 ms 5 ms 100 ms 250 ms 1 ms 5 ms 100 ms 250 ms 666 s 333 s 333 s 333 s 333 s 3 ms 2 ms 2 ms 333 s 1 ms 50 ms 10 ms 333 s 1 ms 40 ms 100 ms 333 s 666 s 666 s 666 s 666 s 2 ms 3 ms 3 ms 666 s 4 ms 50 ms 40 ms 666 s 4 ms 10 ms 150 ms t1 t2
Basic timer 0 carry FF setting pulse Basic timer 1 interrupt pulse
H L H L t1 t2
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11.5 12-Bit Timer
11.5.1 Configuration of 12-bit timer The 12-bit timer consists of a clock select block, 12-bit timer mode control block, count block, overflow detection block, and interrupt control block, as shown in Figure 11-1. 11.5.2 Functional outline of 12-bit timer The count block of the 12-bit timer performs counting operation each time the time selected by the clock select block. If the count value of the count block reaches a specific value, an interrupt request is issued. The function of each block is outlined below. (1) Clock select block This block generates the count clock of the 12-bit timer. The count clock is selected by the timer/counter clock select register (TMCLK: RF address 0CH). This block consists of a divider and selector. (2) 12-bit timer mode control block This block controls the mode of the 12-bit timer. It can control starting and resetting the timer/counter, and select a modulo count mode or free-run count mode. These control operations are performed by using the 12-bit timer mode control register (TMMDCONT: RF address 0EH). (3) Count block The count block counts the count clocks of the timer counter (TMC: peripheral address 47H) and issues an interrupt request when the value of the timer/counter coincides with a predetermined value of the timer modulo register (TMM: peripheral address 46H). (4) Overflow detection block The overflow detection block detects an overflow in the timer/counter in the free-run count mode. To detect the overflow, the timer/counter overflow detect register (TMOVDET: RF address 0DH) is used.
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11.5.3 Divider and selector (1) Configuration of divider and selector Figure 11-14 shows the configuration of the divider and selector. Figure 11-14. Divider and Selector Configuration
Control Register Timer/Counter Clock Select (TMCLK) 0CH b3 T M C K 3 b2 T M C K 2 b1 T M C K 1 b0 T M C K 0
Name
Address Bit
Flag symbol
Selector 1000 s 4.5 MHz Divider 333.3 s 11.1 s 10 s To count block
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(2) Functions of divider and selector The divider and selector divides the system clock (4.5 MHz) and generates the count clock of the 12-bit timer. Four types of the count clock can be selected for different clock frequencies by the timer/counter clock select register. The configuration and function of the timer/counter clock select register are shown below. Configuration and function of timer/count clock select register (TMCLK)
Flag Symbol Name b3 Timer/counter clock select register (TMCLK) T M C K 3 b2 T M C K 2 b1 T M C K 1 b0 T M C K 0 Address
Read/ Write
0CH
R/W
Timer Clock Cycle (Frequency) 0 0 1 1 0 1 0 1 1 ms 333.3 s (1 kHz) (3 kHz)
Measurable Time Range 1 ms - 4095 ms 333.3 s - 1365 ms 10 s - 40.95 ms 11.1 s - 45.5 ms
10 s (100 kHz) 11.1 s (90 kHz)
Fixed to "0"
On reset
Power-ON Clock stop CE
0
0
0 0
0 0
Retained
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11.5.4 12-bit timer mode control block and count block Figure 11-15 shows the configuration of the 12-bit timer mode control block and count block. Figure 11-15. Configuration of 12-Bit Timer Mode Control Block and Count Block
Control Register Address Bit b3 0EH b2 T M R P T b1 T M R E S b0 T M E N Address Symbol Data Buffer (DBF) 0CH DBF3 0DH DBF2 0EH DBF1 0FH DBF0 Address Bit b3 Control Register 3DH b2 b1 b0 I R Q T M b3 I P B T M 1 2FH b2 I P T M b1 I P G R P b0 I P 0
Flag symbol
0
Data
M S B
L S B
Flag symbol
0
0
0
16
16
Peripheral address 47H To overflow detection block Interrupt request signal
Count clock RESET 12-bit timer mode control
Timer/counter
Coincidence detection circuit
Interrupt control
Timer modulo register
Peripheral address 46H
(1) Function of 12-bit timer mode control block The 12-bit timer mode control block controls starting and resetting of the timer/counter and selects an operation mode of the 12-bit timer. The mode is controlled by the 12-bit timer mode control register. How each mode control operation is performed is described below. (a) Start control The timer/counter is started by using the TMEN flag. (b) Reset control The timer/counter is reset by using the TMRES flag. The timer/counter is also reset if a coincidence is detected by the coincidence detection circuit of the count block in the modulo count mode.
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(c) Mode control The operation mode of the 12-bit timer is set by the TMRPT flag. This flag selects two types of modes: free-run count mode and modulo count mode. In the free-run count mode, the contents of the timer/counter is not reset but continues counting even after the value of the timer/counter has coincided with the value of the timer modulo register. In the modulo count mode, the contents of the timer/counter is reset and then continues counting after the value of the timer/counter has coincided with the value of the modulo register. The function and configuration of the 12-bit timer mode control register are shown below.
Flag Symbol Name b3 12-bit timer mode control register (TMMDCONT) b2 T M R P T b1 T M R E S b0 T M E N Address
Read/ Write
0
0EH
R/W
Starts or stops timer/counter 0 1 Stops timer/counter Operates timer/counter
Controls count value of timer/counter 0 1 Not affected Resets timer/counter
Note
Sets mode of 12-bit timer 0 1 Free-run count mode Modulo count mode
Fixed to "0"
On reset
Power-ON Clock stop CE
0
0 0
0 0
0 0
Retained
Note
The TMRES flag is always "0" when read.
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(2) Count block When the count clock is supplied to the timer/counter as shown in Figure 11-15, the timer/counter starts counting. When the value of the timer/counter coincides with the contents of the timer modulo register, an interrupt request signal is output. In the modulo count mode, the timer/counter is reset and then continues counting. The configuration and function of the timer counter and timer modulo register are shown below. (a) Configuration and function of timer/counter The timer/counter counts the count clock. In the free-run count mode, the timer/counter counts up to FFFH, sets the timer counter overflow detect flag to 1 at the next clock, and stops counting. The configuration and function of the timer/counter are shown below. Because the timer/counter is of 12-bit configuration, the lower 12 bits of the data buffer are valid. The higher 4 bits are always "0" when they are read. The timer/counter can be read even during the counting operation. However, the data read at this time may not be accurate. For details, refer to 11.5.7 Error of 12-bit timer.
Name Symbol Address Bit Data b3 DBF3 0CH b2 b1 b0 b3 DBF2 0DH b2 b1 b0 b3 Data Buffer DBF1 0EH b2 b1 b0 b3 DBF0 0FH b2 b1 b0
Transfer data GET 16 Peripheral register
Name
b15 b14 b13 b12 b11 b10 M S B
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0 Symbol L S B
Peripheral address
Peripheral hardware
Timer/counter
Valid data
TMC
47H
Timer/counter
Measured value of timer/counter 0 * Free run-count mode Counts up to FFFH and stops counting at next clock
x
* Modulo count mode Counts up to data value set to timer modulo register and reset to 000H at next clock and counting is restarted
212 - 1 (FFFH) Fixed to "0"
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(b) Configuration and function of timer modulo register The timer modulo register sets reference data to issue an interrupt request when the count value of the timer/counter coincides with its contents. Because this register is a 12-bit register, a value of 1 to 4095 can be set. The coincidence detection circuit detects coincidence between the value set to the timer modulo register and the count value of the timer/counter, and issues an interrupt request. When the interrupt request is issued, the IRQTM flag is set. If the IPTM flag is set in the EI status, the interrupt is accepted, and the program flow is transferred to interrupt vector address 0004H. If data coincidence is detected in the modulo count mode (TMRPT flag = 1), the contents of the timer/ counter are reset. The configuration and function of the timer modulo register are illustrated below. Because the timer modulo register is of 12-bit configuration, the lower 12 bits of the data buffer are valid. The higher 4 bits can be any value when they are written. These bits are always "0" when read.
Name Symbol Address Bit Data b3 DBF3 0CH b2 b1 b0 b3 DBF2 0DH b2 b1 b0 b3 Data Buffer DBF1 0EH b2 b1 b0 b3 DBF0 0FH b2 b1 b0
Transfer data GET 16 PUT Peripheral register
Name Timer modulo register
b15 b14 b13 b12 b11 b10 M S B
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0 Symbol L S B
Peripheral address
Peripheral hardware
Valid data
TMM
46H
Timer modulo
Set value of timer modulo 0 1 Modulo data x Setting prohibited
212 - 1 (FFFH) Fixed to "0"
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11.5.5 Overflow detection block Figure 11-16 shows the configuration of the overflow detection block. The overflow detection block detects an overflow in the timer/counter. When an overflow is detected, the TMOVF flag of the timer/counter overflow detect register is set. When this flag has been set, the counting operation is stopped. Figure 11-16. Configuration of Overflow Detection Block
Control Register Timer/Counter Overflow Detect (TMOVDET) 0DH b3 b2 b1 b0 T M O V F b3
Name
Interrupt Group Select (lGRPSELR)
Group Interrupt Request (lREQGRP)
Interrupt Permission 2 (lNTPM2)
Address Bit
0FH b2 b1 b0 T G R P S L b3 I N T 1
3EH b2 b1 b0 I R Q G R P b3 I P B T M 1
2FH b2 I P T M b1 I P G R P b0 I P 0
Flag symbol
0
0
0
0
0
0
0
0
Count clock
Count block Overflow detection block
Interrupt control block
Issues interrupt request
As shown in Figure 11-16, the overflow of the timer/counter can be used as an interrupt source by using the interrupt group select register (IGRPSELR: RF address 0FH). The configuration and function of the timer/counter overflow detect register and interrupt group select register are shown below.
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(1) Configuration and function of timer/counter overflow detect register
Flag Symbol Name b3 b2 b1 b0 T M O V F Address Read/ Write
Timer/counter overflow detect register (TMOVDET)
0
0
0
0DH
R
Detects overflow of timer/counter 0 1 Does not overflow Overflows
Fixed to "0"
On reset
Power-ON Clock stop CE
0
0
0
0 0
Retained
(2) Configuration and function of interrupt group select register
Flag Symbol Name b3 b2 b1 b0 I G R P S L Address
Read/ Write
Interrupt group select register (lGRPSELR)
0
0
0
0FH
R/W
Sets interrupt source of IRQGRP 0 1 Issues interrupt request at rising or falling edge of INT1 pin Issues interrupt request on overflow of timer/counter
Fixed to "0"
On reset
Power-ON Clock stop CE
0
0
0
0 0 0
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11.5.6 Example of using 12-bit timer Here are examples of using the 12-bit timer: Example 1. Modulo count mode TMINT ORG DAT BR TMINT Processing A EI RETI START: INITFLG TMCK1, NOT TMCK0 ; Sets count clock to 10 s MOV MOV MOV PUT SET1 EI SET3 LOOP: Main processing BR LOOP This program executes processing A every 500 s. However, processing A must be completed shorter than 500 s. TMRPT, TMRES, TMEN DBF2, #50 SHR 8 AND 0FH DBF1, #50 SHR 4 AND 0FH DBF0, #50 AND 0FH TMM, DBF IPTM 0004H START ; Program address (0004H) ; Symbol definition of 12-bit timer/counter interrupt vector address
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Example 2. Free-run count mode BR ... Start INITFLG TMCK1, NOT TMCK0 ; Sets count clock to 10 s INITFLG NOT TMRPT, TMRES, TMEN Processing A SKF1 BR GET ... Overflows : ... This program measures the time required to perform processing A. The time can be set from 10 s to 40950 s (in the above example, the time 40950 s or longer cannot be measured, and therefore, execution branches by software to another routine). This program is used to measure the pulse width of a remote controller signal. To issue an interrupt request at fixed time intervals, the modulo count mode is convenient. To measure a total time, however, the free-running count mode is convenient. TMOVF Overflows DBF, TMC Start
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11.5.7 Error of 12-bit timer An error of the interrupt by the timer occurs in the following cases: (1) When the TMEN flag is set to 1 (2) When the timer/counter is reset (3) When the data of the timer/counter is read during counting operation Figure 11-17 illustrates the error that may occur during operation. Figure 11-17. Error of 12-Bit Timer (1/2) (1) When TMEN flag is set to 1
H L Error tSET 1 0 1 0 1 0 EI DI EI <1> SET1 TMEN Interrupt accepted EI Interrupt accepted tSET
Clock
TMEN
IRQTM
IPTM
INTE FF
Remark fSET = (Data set to timer modulo register) x (Count clock) If the timer modulo register operates with the TMEN flag set in<1> above, the timer/counter is incremented at the falling edge of the clock, and an interrupt request is issued when the contents of the timer/counter coincide with those of the timer modulo register. Depending on the timing at which the TMEN flag is set to 1, the error of the interrupt request issuance varies as follows: 0 (error) < (one cycle of count clock)
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Figure 11-17. Error of 12-Bit Timer (2/2) (2) When timer/counter is reset
Clock H L Error tSET 1 0 1 0 1 0 EI DI EI <1> SET1 TMRES Interrupt accepted EI Interrupt accepted tSET
TMRES
IRQTM
IPTM
INTE FF
Remark tSET = (Data set to timer modulo register) x (Count clock) If the TMRES flag is set in <1> above, the contents of the timer/counter are reset, and the timer/counter is incremented at the falling edge of the next clock. When the contents of the timer/counter coincide with those of the timer modulo register, an interrupt request is issued. Depending on the timing at which the TMRES flag is set to 1 at this time, the error of interrupt request issuance varies as follows: 0 (error) < (one cycle of count clock) (3) When data of timer/counter is read during counting operation
H L
Clock
Reset signal
H L <1>
Error
<2> GET DBF, TMC
When the data of the timer/counter is read in <1> and <2> above, the result is the same data in both the cases. Therefore, the error when the data of the timer/counter is read is as follows: 0 (error) (one cycle of count clock)
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11.5.8 Notes on using 12-bit timer The interrupt by the 12-bit timer may occur at the same time as the CE reset or basic timer 1 interrupt. Therefore, if time control, such as watch processing, is necessary at CE reset, do not use the 12-bit timer but use the basic timer 0 carry or basic timer 1 interrupt. When using the 12-bit timer in combination with the basic timer 1 interrupt, pay attention to the priorities.
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12. STANDBY
The standby function is used to reduce the current dissipation of the device during back up.
12.1 Configuration of Standby Block
Figure 12-1 shows the configuration of the standby block. As shown in this figure, the standby block is divided into two subblocks: halt control block and clock stop control block. The halt control block consists of a halt control circuit, interrupt control block, basic timer 0 carry, and the P0D0/ ADC2 through P0D3/ADC5 key input pins, and controls the operation of the CPU (program counter, instruction decoder, and ALU block). The clock stop control block has a clock stop control circuit that controls the 4.5-MHz crystal oscillator circuit, CPU, system registers, and control registers. Figure 12-1. Configuration of Standby Block
Halt block Interrupt block Basic timer 0 carry
Input latch
Halt control circuit HALT h
CPU
Program counter (PC)
P0D3/ADC5 pin P0D2/ADC4 pin P0D1/ADC3 pin P0D0/ADC2 pin
Instruction decoder ALU
Clock stop block CE pin XOUT pin XIN pin Internal block Clock stop control circuit
System register Control register
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12.2 Standby Function
The standby function reduces the current dissipation of the device by stopping part of or entire device operation. The standby function is divided into a halt function and clock stop function. The halt function reduces the current dissipation of the device by stopping the operation of the CPU by using a dedicated instruction "HALT h". The clock stop function reduces the current dissipation of the device by stopping the 4.5-MHz crystal oscillation circuit by using a dedicated instruction "STOP s". In addition to the halt and clock stop functions, the CE pin is also used to set an operation mode of the device. The CE pin is used to control the operation of the PLL frequency synthesizer and to reset the device, and therefore, can be said to be one of the standby functions. 12.3 below describes how device operation modes are set by the CE pin. 12.4 and 12.5 respectively describe the halt function and clock stop function.
12.3 Device Operation Mode Set by CE Pin
The CE pin controls the following functions (1) through (3) depending on the input level of and the rising edge of an externally input signal. (1) Operation control of PLL frequency synthesizer (2) Validation control of clock stop instruction (3) Device reset The following 12.3.1 through 12.3.3 describe (1) through (3) above. 12.3.1 Operation control of PLL frequency synthesizer The PLL frequency synthesizer can operate only while the CE pin is high. While the CE pin is low, the frequency synthesizer is automatically disabled. In the PLL disable status, the VCOH and VCOL pins are internally pulled down, and the EO0 and EO1 pins are floated. The PLL frequency synthesizer can be disabled by program even when the CE pin is high. 12.3.2 Validation control of clock stop instruction The clock stop instruction "STOP s" is valid only when the CE pin is low. The "STOP s" instruction executed when the CE pin is high is excuted as a no-operation (NOP) instruction. 12.3.3 Device reset By asserting the CE pin high, the device can be reset (CE reset). In addition to CE reset, power-ON reset can be also performed on application of supply voltage VDD. For details, refer to 13. RESET.
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12.3.4 Signal input to CE pin The CE pin does not accept a low level or high level of less than 110 to 165 s to prevent malfunctioning due to noise. The level of the signal input to the CE pin can be detected by the CE flag of the CE pin level judge register (RF address 07H). Figure 12-2 shows the relation between the input signal and CE flag. Figure 12-2. Relation between CE Pin Input Signal and CE Flag
CE pin CE flag H L 1 0 110-165 s Less than 110 to 165 s 110-165 s CE reset PLL disabled STOP s instruction invalidated (NOP). CE reset is effected in synchronization with next setting of basic timer 0 carry FF.
Less than 110 to 165 s
PLL operation enabled STOP s instruction invalidated (NOP)
PLL disabled STOP s instruction validated
12.3.5 Configuration and function of CE pin level judge register The CE pin level judge register detects the input signal level of the CE pin. The configuration and function of this register are shown below.
Flag Symbol Name b3 CE pin level judge register (CEJDG) b2 b1 b0 C E Address
Read/ Write
0
0
0
07H
R
Detects level input to CE pin 0 1 Low level is input High level is input
Fixed to "0"
On reset
Power-ON Clock stop CE
0
0
0
- - -
The CE flag is not affected by a low or high level of less than 110 to 165 s.
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12.4 Halt Function
The halt function stops the operation clock of the CPU by executing the "HALT h" instruction. When this instruction is executed, the program is stopped, until the halt status is later released. The power dissipation of the device in the halt status is reduced by the operation current of the CPU. The halt status is released by key input, basic timer 0 carry, and interrupt. The release condition of the key input, basic timer 0 carry, and interrupt is specified by the operand "h" of the "HALT h" instruction. The "HALT h" instruction is valid regardless of the input level of the CE pin. The following 12.4.1 through 12.4.6 describe the halt status and halt release conditions. 12.4.1 Halt status In the halt status, all the operations of the CPU are stopped. In other words, program execution is stopped at the "HALT h" instruction. However, the peripheral hardware continues the operation set before the "HALT h" instruction is executed. For the operation of the peripheral hardware, refer to 12.6 Device Operation in Halt and Clock Stop Status.
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12.4.2 Halt releasing condition Figure 12-3 shows the halt release conditions. As shown in this figure, the halt release conditions are set by the 4-bit data specified by the operand "h" of the "HALT h" instruction. The halt status is released when a condition specified by "1" in operand "h" is satisfied. When the halt status is released, execution is started from the instruction next to the "HALT h" instruction. If two or more release conditions are set, the halt status is released if one of the set conditions is satisfied. When the device is reset (power-ON reset or CE reset), the halt status is released, and the reset operation is performed. If 0000B is set as halt release condition "h", no release condition is set. At this time, the halt status is released when the device is reset (power-ON reset or CE reset). The following 12.4.3 through 12.4.5 describe the halt release conditions by key input, basic timer 0 carry, and interrupt, respectively. 12.4.6 shows an example where two or more release conditions are set. Figure 12-3. Halt Release Condition
HALT h (4 bit) Operand bit b3 b2 b1 b0
Sets halt status release condition Released when high level is input to P0D pin (P0D3/ADC5-P0D0/ADC2 pin) Released when basic timer 0 carry FF is set to 1 Undefined (fix to "0") Released when interrupt (lNT0 pin, INT1 pin, timer/counter overflow, 12-bit timer, basic timer 1, serial interface 0, and frequency counter) is accepted 0 1 Not released even if condition is satisfied Released if condition is satisfied
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12.4.3 Releasing halt by key input Releasing the halt status by key input is set by the "HALT 0001B" instruction. When releasing the HALT condition by key input is set, the halt status is released if a high level is input to any one of the P0D0/ADC2 to P0D3/ADC5 pins. The following paragraphs (1) through (4) describe the points to be noted when a general-purpose output port is used as a key source signal, when LCD segment signal output is multiplexed with key source signal output, and when the P0D0/ADC2 through P0D3/ADC5 pins are used as A/D converter pins. (1) Notes on using general-purpose output port as key source signal
P0D3/ADC5 Latch P0D2/ADC4 P0D1/ADC3 Switch A P0D0/ADC2 General-purpose output port
After the general-purpose output port for key source signal is asserted high level, the "HALT 0001B" instruction is executed. If an alternate switch such as A in the above figure is used, a high level is always applied to the P0D0/ADC2 pin while switch A is closed. Consequently, the halt status is released immediately. Therefore, exercise care when using an alternate switch. To use a general-purpose output port as a key source signal, reset the KSEN flag of the LCD mode select register (LCDMODE: RF address 10H) to "0". At this time, the P0D0/ADC2 through P0D3/ADC5 pins are automatically pulled down internally.
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(2) Notes on multiplexing LCD segment signal output with key source signal output
P0D3/ADC5 Latch P0D2/ADC4 P0D1/ADC3 P0D0/ADC2 LCD15/P0Y15/KS15
LCD segment signal LCD segment signal H output wave form L 220 s Key source signal
After setting the key source signal output data, execute the "HALT 0001B" instruction. If the key source signal output data is "0" at this time, the halt status is not released even if the high level of an LCD segment signal is input to the pin. To multiplex LCD segment signal output with key source signal output, set the KSEN flag of the LCD mode select register to 1. The key source signal data (setting a pin that outputs the key source) is set by the key source data register (KSR: peripheral address 42H) via data buffer. When the LCD segment signal output is multiplexed with key source signal output, the internal key latch circuit latches data only while the key source signal is output, and is disconnected from the external source while the LCD segment signal is output. The internal pull-down resistor is ON only while the key source signal is output.
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(3) Notes on using P0D0/ADC2 through P0D3/ADC5 pins as A/D converter pins
A/D input
P0D3/ADC5 P0D2/ADC4 P0D1/ADC3 P0D0/ADC2
A/D input Latch
General-purpose output port or LCD segment signal output
When any of the P0D0/ADC2 through P0D3/ADC5 pins is selected as the A/D converter pins, the selected pin (only one pin can be selected at a time) is disconnected from the input latch and connected to the internal A/D converter. If a high level happens to be input to the pin when the pin is selected to the A/D converter, the latch circuit retains the high level If the "HALT 0001B" instruction is executed in this status, the halt status is immediately released because the input latch is high. To avoid this, set the input port mode before executing the "HALT 0001B" instruction, and inputs a low level to the A/D converter. (4) Others
P0D3/ADC5 Output port P0D2/ADC4 Microcontroller, etc. P0D1/ADC3 P0D0/ADC2 General-purpose output port or LCD segment signal output Latch
The P0D0/ADC2 through P0D3/ADC5 pins can be used as general-purpose input port pins with pull-down resistor. Therefore, the halt status can also be released by another microcontroller as shown above.
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12.4.4 Releasing halt status by basic timer 0 carry Releasing the halt status by using the basic timer 0 carry is set by the "HALT 0010B" instruction. When releasing the halt status by using the basic timer 0 carry is set, the halt status is released as soon as the basic timer 0 carry FF has been set to 1. The basic timer 0 carry FF corresponds to the BTM0CY flag of the basic timer 0 carry FF judge register on a oneto-one basis, as described in 11. TIMER FUNCTION, and is set to 1 at fixed time intervals (1, 5, 100, or 250 ms). Therefore, the halt status can be released at fixed time intervals. Here is an example: Example M1 MEM 0.10H ; 1-second counter ; Symbol definition ; Embedded macro ; Sets basic timer 0 carry FF setting time to 250 ms LOOP: HALT SKT1 BR ADD SKT1 BR BR HLTBTME BTM0CY LOOP M1, #0100B CY LOOP Processing A LOOP In this example, the halt status is released every 250 ms, and processing A is executed every 1 second. ; Setting basic timer 0 carry FF as halt release condition ; Embedded macro ; Branches to LOOP if BTM0CY flag is not set ; Adds 0100B to contents of M1 ; Embedded macro ; Executes processing A if carry occurs
HLTBTMR DAT 0010B INITFLG NOT BTM0CK1, BTM0CK0
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12.4.5 Releasing halt status by interrupt Releasing the halt status by an interrupt is set by the "HALT 1000B" instruction. When releasing the halt status by an interrupt is set, the halt status is released as soon as the interrupt is accepted. There are the following six interrupt sources available (refer to 10. INTERRUPT): * INT0 pin * INT1 pin or timer/counter overflow * 12-bit timer * Basic timer 1 * Serial interface 0 * Frequency counter Therefore, which interrupt source is used to release the halt status must be specified in advance by program. To accept an interrupt, the interrupt request must be issued from each interrupt source, all the interrupts must be enabled (by the EI instruction), and each interrupt must be enabled (the corresponding interrupt permission flag must be set). Even if an interrupt request is issued, therefore, if the interrupt is not enabled, the interrupt is not accepted, and the halt status is not released. When the halt status is released by accepting an interrupt, the program flow is transferred to the vector address of the interrupt. When the "RETI" instruction is executed after the interrupt processing, the program flow is restored to the instruction next to the "HALT" instruction. An example is given below.
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Example HLTINT INT0PIN START: BR ORG ORG INTBTM1 BR INT0PIN Processing A BR INTBTIMER1: Processing B EI_RETI: EI RETI MAIN: SET2 SET2 IPBTM1, IP0 ; Embedded macro BTMCK3, BTMCK2 ; Embedded macro ; Sets time interval of timer interrupt to 1 ms LOOP: Processing C EI HALT ; <1> BR LOOP HLTINT ; Main routine processing ; Enables all interrupts ; Sets releasing halt status by interrupt ; Interrupt processing by timer EI_RETI INTBTIMER1 ; INT0 pin interrupt vector address (0006H) ; Interrupt processing by INT0 pin MAIN ; Timer interrupt vector address (0003H) DAT DAT 1000B 0003H 0006H ; Symbol definition of halt condition ; Interrupt vector address symbol definition ; Interrupt vector address symbol definition ; Program address 0000H INTBTM1 DAT
In the above example, the halt status is released when the interrupt by the basic timer 1 is accepted, and processing B is executed. When the interrupt by the INT0 pin is accepted, processing A is executed. Each time the halt status is released, processing C is executed. If the interrupt request by the INT0 pin and the interrupt request by the basic timer 1 are issued exactly at the same time in the halt status, the processing A of the INT0 pin which has the higher hardware priority is executed. If the "RETI" instruction is executed after processing A has been executed, execution is restored to the "BR LOOP" instruction in <1>, but the "BR LOOP" instruction is not executed, and the basic timer 1 interrupt is immediately accepted. If the "RETI" instruction is executed after the processing B of the basic timer 1 interrupt processing has been executed, the "BR LOOP" instruction is executed.
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Caution To execute the HALT instruction whose release condition is setting the interrupt request flag (IRQxxx) with the corresponding interrupt permission flag (IPxxx) set, describe a NOP instruction immediately before the HALT instruction. If the NOP instruction is described immediately before the HALT instruction, time of one instruction is generated between the IRQxxx manipulation instruction and HALT instruction. When the CLR1 IRQxxx instruction is executed, for example, clearing IRQxxx is correctly reflected on the HALT instruction (Example 1). If the NOP instruction is not described immediately before the HALT instruction, the CLR1 IRQxxx instruction is not reflected on the HALT instruction, and the HALT mode is not set (Example 2). Example 1. Program that correctly executes HALT instruction ... ...... CLR1 NOP HALT ...... 2. Program that does not set HALT mode ... ...... CLR1 HALT ...... IRQxxx 1000B ; Setting of IRQxxx ; Clearing IRQxxx is not reflected on HALT instruction ; (reflected on instruction next to HALT instruction) ; HALT instruction is ignored (HALT mode is not set) 1000B IRQxxx ; Describe NOP instruction immediately before HALT instruction ; (clearing IRQxxx is correctly reflected on HALT instruction ; Correctly executes HALT instruction (HALT mode is set) ; Setting of IRQxxx
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12.4.6 If two or more release conditions are set simultaneously If two or more halt release conditions are set at the same time, the halt status is released if even one of the set conditions is satisfied. The following examples indicate how release conditions is identified when two or more release conditions are satisfied at once. Example 1. HLTINT HLTBTMR HLTKEY INT0PIN START: BR ORG: INT0PIN Processing A EI RETI BTMRUP: Processing B RET KEYDEC: Processing C RET MAIN MOVT PUT SET2 DBF, @AR KSR, DBF KSEN, LCDEN ; Embedded macro ; Multiplexes LCD segment signal output with key source ; signal output SET2 SET1 EI LOOP: HALT HLTINT OR HLTBTMR OR HLTKEY ; Sets interrupt, basic timer 0 carry, and key in ; put as halt releasing conditions SKF1 CALL SKF1 CALL BR BTM0CY BTMRUP KEYJ KEYDEC LOOP ; Embedded macro ; Detects BTM0CY flag ; Basic timer 0 carry processing if BTM0CY flag is set ; Embedded macro ; Detects key input latch ; Key input processing if latched BTM0CK1, BTM0CK0 IP0 ; Embedded macro ; Sets basic timer 0 carry FF setting time to 1 ms ; Embedded macro ; Enables INT0 pin interrupt ; Sets key source output data (table reference) to ; key source data register (KSR) ; Key input processing ; Basic timer 0 carry processing ; INT0 pin interrupt processing MAIN DAT 1000B DAT 0010B DAT 0001B DAT 0006H ; INT0 pin interrupt vector address symbol definition
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In example 1 above, the INT0 pin interrupt, 1-ms basic timer 0 carry, and key input are set as the halt status releasing conditions. To identify the condition responsible for releasing the halt status, a vector address is detected if the halt status is released by an interrupt, the BTM0CY flag is detected if the halt status is released by the basic timer 0 carry, and the KEYJ flag is detected if the halt status is released by key input. When using two or more releasing conditions, the following two points must be noted: (1) All the set release conditions must be detected when the halt status is released. (2) The release conditions are detected according to their priorities. Care must be exercised if the program after "MAIN" in Example 1 above is as shown in Example 2 below. Do not create the following program if the priority of the timer by timer carry is high. Example 2. MAIN: SET4 SET2 SET1 EI LOOP: HALT SKF4 BR SKF1 CALL BR KEYDEC: Processing C BR LOOP HLTINT OR HLTBTMR OR HLTKEY P0D3, P0D2, P0D1, P0D0 KEYDEC BTM0CY BTMRUP LOOP ; Key input processing ; Detects key input P1C3, P1C2, P1C1, P1C0 BTM0CK1, BTM0CK0 IP0 ; Uses general-purpose output port as key source signal
Suppose that the halt status is released by key input in Example 2 above, and that the basic timer 0 carry FF is set to 1 immediately after that. Then the program executes the "HALT" instruction again after executing the key input processing. The halt status is immediately released because the basic timer 0 carry FF is set. However, because a high level of about 100 ms is usually input as key input, execution branches to the key input processing. Consequently, the basic timer 0 carry FF is not correctly detected.
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12.5 Clock Stop Function
The clock stop function stops the 4.5-MHz crystal oscillation circuit by executing the "STOP s" instruction (clock stop status). Therefore, the current dissipation of the device is reduced down to 5 A MAX. For the details of the current dissipation, refer to 12.7 Current Dissipation in Halt and Clock Stop Status. Specify "000B" as the operand "s" of the "STOP s" instruction. The "STOP s" instruction is valid only when the CE pin is low, and is executed as a no-operation (NOP) instruction when the CE pin is high. Therefore, the "STOP s" instruction must be executed when the CE pin is low. The clock stop status is released by asserting the CE pin high (CE reset). The following 12.5.1 through 12.5.3 describe the clock stop status, how to release the clock stop status, and notes on using the clock stop instruction. 12.5.1 Clock stop status Because the crystal oscillation circuit is stopped in the clock stop status, all the device operations, such as the CPU and peripheral hardware, are stopped. For the operations of the CPU and peripheral hardware, refer to 12.6 Device Operation in Halt and Clock Stop Status. In the clock stop status, the power failure detection circuit does not operate even if the supply voltage VDD of the device is lowered to 2.2 V. Therefore, the data memory can be backed up at a low voltage. For the details of the power failure detection circuit, refer to 13. RESET. 12.5.2 Releasing clock stop status The clock stop status is released by asserting the CE pin high (CE reset) or lowering the device supply voltage VDD to 2.2 V once and then increasing it to 4.5 V (power-ON reset). Figures 12-4 and 12-5 show the releasing operation at CE reset and power-ON reset, respectively. When the clock stop status is released by power-ON reset, the power failure detection circuit operates. For the details of the power-ON reset, refer to 13.4 Power-ON Reset.
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Figure 12-4. Releasing Clock Stop Status by CE Reset
5V VDD 0V H CE pin L H XOUT Pin L
Approx. 50 ms
STOP s instruction
Program starts from address 0 (CE reset)
5V VDD 0V H CE pin L H XOUT Pin L
Operation is as follows if clock stop instruction is not used.
0 - tSET Program starts from address 0 (CE reset) CE reset is effected in synchronization with next setting of basic timer 0 carry FF after CE pin goes high
Figure 12-5. Releasing Clock Stop Status by Power-ON Reset
5V VDD 0V H CE pin L H
XOUT Pin L
Approx. 50 ms
2.2 V
STOP s instruction
Program starts from address 0 (power-ON reset)
5V VDD 0V H CE pin L H XOUT Pin L
Operation is as follows if clock stop instruction is not used. 3.5 V
Approx. 50 ms
Oscillation stops
Program starts from address 0 (power-ON reset)
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12.5.3 Notes on using clock stop instruction The clock stop instruction (STOP s) is valid only when the CE pin is low. Therefore, processing to be performed when the CE pin happens to be high must be considered in the program. Here is an example: Example XTAL CEJDG: ; <1> SKF1 BR ; <2> STOP ; <3> BR MAIN: Main processing BR CEJDG $-1 XTAL ; Clock stop CE MAIN Processing A ; Embedded macro ; Detects input level of CE pin ; If CE = high, branches to main processing ; Processing when CE = low DAT 0000B ; Symbol definition of clock stop condition
In the above example, the status of the CE pin is detected in <1>. If the CE pin is low, processing A is executed, and then the clock stop instruction in <2>, "STOP XTAL", is executed. If the CE pin goes high while the "STOP XTAL" instruction in <2> is executed as shown in the figure below, the "STOP XTAL" instruction operates as a no-operation (NOP) instruction. At this time, without a branch instruction of <3> "BR $-1", the program might malfunction by branching to the main processing. It is therefore necessary to insert a branch instruction as in <3> or to create a program that does not malfunction even if execution branches to the main processing. If a branch instruction is used as in <3>, CE reset is effected in synchronization with the next setting of the basic timer 0 carry FF even if the CE pin remains high.
5V VDD 0V H CE pin L Main Processing A processing <1><1><1> Detects CE pin <2> STOP XTAL Program starts from address 0 Treated as NOP instruction in synchronization with setting because CE pin is high at of basic timer 0 carry FF (CE reset). this time.
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12.6 Device Operation in Halt and Clock Stop Status
Table 12-1 shows the operations of the CPU and peripheral hardware in the halt and clock stop statuses. As shown in this table, all the peripheral hardware continues the normal operation in the halt status, but instruction execution is stopped. In the clock stop status, all the peripheral hardware stops operation. The control registers that control the operations of the peripheral hardware operate normally in the halt status (not initialized) but are initialized to predetermined values in the clock stop status (when the STOP s instruction is executed). In other words, the peripheral hardware continues the operation set by the control registers in the halt status. In the clock stop status, the operations of the peripheral hardware are determined by the control registers that have been initialized to predetermined values. For the values to which the control registers are to be initialized, refer to 8. REGISTER FILE (RF). Here is an example: Example To set P0A3/SDA and P0A2/SCL pins of port 0A in output port mode and use P0A1/SCK0 and P0A0/ SO0 pins as serial interface lines HLTINT XTAL DAT DAT 1000B 0000B ; Symbol definition ; ; Embedded macro ; <1> SET2 P0A3, P0A2 ; ; SET2 ; <2> INITFLG NOT SIO0IMD1, SIO0IMD0 CLR1 SET1 EI ; <3> SET1 ; <4> HALT ; <5> STOP XTAL HLTINT SIO0NWT IRQSIO0 IPSIO0 SIO0CK1, SIO0CK0 INITFLG SIO0CH, NOT SB, SIO0MS, SIO0TX
INITFLG P0ABIO3, P0ABIO2, P0ABIO1, P0ABIO0
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In the above example, the P0A3 and P0A2 pins output a high level in <1>, the conditions of the serial interface 0 are set in <2>, and serial communication is started in <3>. If the "HALT" instruction is executed in <4> at this time, serial communication is continued. The halt status is released when the interrupt by the serial interface 0 is accepted. If the "STOP" instruction is executed in <5> instead of the "HALT" instruction in <4>, all the flags of the control registers set in <1>, <2>, and <3> are initialized when the "STOP" instruction is executed. Consequently, serial communication is stopped, and all the pins of port 0A are set in the general-purpose input port mode. Table 12-1. Device Operation in Halt and Clock Stop Status
Status Peripheral Hardware CE Pin = High Level Halt Program counter Stops at address of HALT instruction System register Peripheral register Control register 12-bit timer Basic timer PLL frequency synthesizer A/D converter D/A converter Clock generator port Serial interface Frequency counter LCD controller/driver Key source controller/decoder General-purpose I/O port General-purpose input port General-purpose output port Retained Retained Retained Normal operation Normal operation Normal operation Normal operation Normal operation Normal operation Normal operation Normal operation Normal operation Normal operation Normal operation Normal operation Normal operation Clock Stop STOP instruction is invalid (NOP) CE Pin = Low Level Halt Stops at address of HALT instruction Retained Retained Retained Normal operation Normal operation Disabled Normal operation Normal operation Normal operation Normal operation Normal operation Normal operation Normal operation Normal operation Normal operation Normal operation Clock Stop Initialized to 0000H and stops InitializedNote Retained InitializedNote Operation stopped Operation stopped Operation stopped Operation stopped Operation stopped Operation stopped Operation stopped Operation stopped Operation stopped Operation stopped Input port Input port Retained
Note
For the values to which the control registers are to be initialized, refer to 5. SYSTEM REGISTER (SYSREG) and 8. REGISTER FILE (RF).
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12.7 Current Dissipation in Halt and Clock Stop Status
12.7.1 Device current dissipation in halt status Figure 12-6 shows the device current dissipation IDD in the halt status. The numbers (1) through (4) in this figure indicate current dissipation when each of the four types of programs below is executed. As shown in Figure 12-6, the less often the halt status is released, the lower the current dissipation is. (1) Program 1 The HALT instruction is not used. Example NOP BR (2) Program 2 The 5-ms basic timer 1 interrupt is set as the halt release condition, and 20 instructions (about 90 s) are executed each time the halt status is released. Example HLTINT DAT 1000B 0003H LOOP INTBTM1 DAT BR ORG REPT ENDR EI RETI LOOP: INITFLG SET1 EI HALT BR HLTINT $-1 BTM1CK1, NOT BTM1CK0 IPBTM1 BTM1INT 17 NOP $-1
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(3) Program 3 The 100-ms basic timer 1 interrupt is set as the halt rlease condition, and 20 instructions are executed each time the halt status is released. Example HLTINT DAT 1000B 0003H LOOP INTBTM1 DAT BR ORG REPT ENDR EI RETI LOOP: CLR2 SET1 EI HALT BR (4) Program 4 Nothing is set as the halt release condition. Example HLTNORLS DAT 0000B HALT HLTNORLS The device current dissipation IDD shown in Figure 12-6 is measured under the following conditions: * PLL is disabled. * Frequency counter is disabled. * Sine wave with a frequency fIN = 4.5 MHz and input amplitude VIN = VDD to the XIN pin from a standard signal generator. * All the pins set in the output mode are open. * All the pins set in the input port (except the XIN pin) are pulled down with a 47-K resistor. 12.7.2 Device current dissipation in clock stop status Figure 12-7 shows the device current dissipation IDD in the clock stop status. The current dissipation shown in Figure 12-7 is measured under the following conditions: * All the pins set in the output mode are open. * All the pins set in the input mode (except the XIN pin) are pulled down with a 47-K resistor. * A crystal resonator is connected (oscillation is stopped, however). HLTINT $-1 BTM1CK1, BTM1CK0 IPBTM1 BTM1INT 17 NOP
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Figure 12-6. Device Current Dissipation in Halt Status (reference) (a) IDD vs. VDD (Ta = 25C)
1.5 (1) 1.5
(b) IDD vs. Ta (VDD = 5.5 V)
Current dissipation IDD (mA)
Current dissipation IDD (mA)
(1)
1.0
1.0
0.5
(2) (3)
0.5
(2) (3)
0
3.5
4.0
4.5
5.0
5.5
0
-40
0
25
85
Supply voltage VDD (V)
Ambient temperature Ta (C)
Figure 12-7. Device Current Dissipation in Clock Stop Status (reference) (a) IDD vs. VDD (Ta = 25C)
Current dissipation IDD ( A) Current dissipation IDD ( A)
3.0 3.0
(b) IDD vs. Ta (VDD = 5.5 V)
2.0
2.0
1.0
1.0
0
2.2 2.5
3.0
3.5
4.0
4.5
5.0
5.5
0
-40
0
25
85
Supply voltage VDD (V)
Ambient temperature Ta (C)
12.7.3 Notes on processing of each pin in halt and clock stop statuses The halt status is used to reduce the current dissipation when, for example, only the watch operates. The clock stop function is used to reduce the current dissipation when only the contents of the data memory are to be retained. Therefore, the current dissipation must be minimized in the halt and clock stop statuses. The current dissipation substantially changes depending on the status of each pin. Therefore, remember the points indicated in Table 12-2.
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Table 12-2. Notes on Status of Each Pin in Halt and Clock Stop Statuses (1/2)
Pin Function Pin Symbol Pin Status and Notes on Processing Halt Status General-purpose I/O port Port 0A P0A3/SDA P0A2/SCL P0A1/SCK0 P0A0/SO0 Port 0B P0B3/SI0 P0B2/SCK1 P0B1/SO1 P0B0/SI1 Port 0C P0C3 P0C2 P0C1 P0C0 Port 1A P1A3 P1A2 P1A1 P1A0/FCG General-purpose input port Port 0D P0D3/ACD5 P0D2/ASC4 P0D1/ADC3 P0D0/ACD2 Port 1D P1D3/FMIFC P1D2/AMIFC P1D1/ADC1 P1D0/ADC0 General-purpose output port Port 1B P1B3/PWM2 P1B2/PWM1 P1B1/PWM0 P1B0/CGP Port 1C P1C3 P1C2 P1C1 P1C0 Port 2A Interrupt Status before halt status is set is retained. (1) When specified as output pin Current dissipation increases if these pins are externally pulled down while they output high level, or externally pulled up while they output low level. Exercise care in using N-ch open-drain output pins (P0A3, P0A2, P1B3-P1B0). (2) When specified as input pin (except ports 1A and 1D) Current dissipation increases due to noise if these pins are floated. (3) Port 0D (P0D3/ADC5-P0D0/ADC2) Current dissipation increases if these pins are externally pulled up because they are connected to internal pull-down resistor. However, pull-down resistor is disconnected from pins selected as A/D converter pins. (4) Ports 1D (P1D3/FMIFC-P1D0/ ADC0) and 1A (P1A3-P1A0/FCG) When P1D3/FMIFC and P1D2/ AMIFC pins are used as IF counter pins, internal amplifier operates and current dissipation increases. Because IF counter is not automatically disabled even if CE pin goes low, initialize it by program as necessary. Power dissipation of ports 1D and 1A does not increase due to noise even if they are floated as general-purpose input port. Specified as general-purpose output port. Output contents are retained as is. Therefore, current dissipation increases if these pins are externally pulled down while high level is output or pulled up while low level is output. Clock Stop Status All pins are specified as general-purpose input port. Current dissipation of all input port pins, except port 0C (P0C3-P0C0), does not increase due to noise even if they are floated externally. Port 0C (P0C3-P0C0) must be externally pulled down or up so that current dissipation does not increase due to noise. Port 0D (P0D3/ADC5-P0D0/ADC2) is internally pulled down.
P2A0
INT1 INT0 Current dissipation increases due to external noise when these pins are floated.
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Table 12-2. Notes on Status of Each Pin in Halt and Clock Stop Statuses (2/2)
Pin Function Pin Symbol Pin Status and Notes on Processing Halt Status LCD segment LCD29/P0F3 | LCD26/P0F0 LCD25/P0E3 | LCD22/P0E0 LCD21/P0X5 | LCD16/P0X0 LCD15/P0Y15/KS15 | LCD0/POY0/KS0 PLL frequency synthesizer VCOL VCOH EO0 EO1 Current dissipation increases while PLL operates. When PLL is disabled, status of each pin is as follows: VCOL, VCOH Internally pulled down EO0, EO1 Floated EO0, EO1 PLL is disabled. Status of each pin is as follows: VCOL, VCOH Internally pulled down Floated When these pins are used as general-purpose output port pins, bear in mind same points as general-purpose port pins described earlier. Current dissipation increases via port 0D (connected with pull-down resistor) when key source signals are output and if there is switch that is always ON, such as transistor switch and if "1" is output as key source data. Clock Stop Status All pins are specified as LCD segment signal output pins and output low level (display off).
When CE pin goes low, PLL is automatically disabled. Crystal oscillation circuit XIN XOUT Current dissipation changes depending on oscillation waveform of crystal oscillation circuit. The greater the oscillation amplitude, the lower the current dissipation. Oscillation amplitude is affected by crystal oscillator to be used or load capacitor, and must be evaluated. XIN pin is internally pulled down, and XOUT pin outputs high level.
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13. RESET
The reset function is used to initialize the device operation.
13.1 Configuration of Reset Block
Figure 13-1 shows the configuration of the reset block. The device is reset in two ways: power-ON reset or VDD reset that is executed by applying supply voltage VDD, and CE reset that is executed by using the CE pin. The power-ON reset block consists of a voltage detection circuit that detects the voltage input to the VDD pin, a power failure detection circuit, and a reset control circuit. The CE reset block consists of a circuit that detects the rising of the signal input to the CE pin and a reset control circuit. Figure 13-1. Configuration of Reset Block
XOUT XIN Reads BTM0CY flag STOP s instruction R Q S Basic timer 0 carry disable FF Power-ON clear signal (POC) Reset control circuit Basic timer 0 carry Power failure detection block Timer FF block Divider Selector
VDD
Voltage detection circuit Rising detection circuit
Reset signal IRES RES RESET
Forced halt by basic timer 0 carry Control register, system register, stack, program counter
CE
STOP instruction
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13.2 Reset Function
Power-ON reset is executed when the supply voltage VDD rises from a specific level, and CE reset is executed when the CE pin goes high. Power-ON reset initializes the program counter, stack, system registers, and control registers, and executes the program from address 0000H. CE reset initializes the program counter, stack, system registers, and some control registers, and executes the program from address 0000H. The difference between power-ON reset and CE reset lies in the control registers that are initialized, and the operation of the power failure detection circuit described in 13.6. Power-ON reset and CE reset are controlled by the reset signals IRES, RES, and RESET that are output by the reset control circuit shown in Figure 13-1. Table 13-1 shows the relations among the IRES, RES, and RESET signals, and power-ON reset and CE reset. The reset control circuit also operates when the clock stop instruction (STOP s) described in 12. STANDBY is executed. The following 13.3 and 13.4 respectively describe CE reset and power-ON reset. 13.5 describes the relation between CE reset and power-ON reset. Table 13-1. Relations among Internal Reset Signals and Reset Operations
Internal Reset Signal IRES On CE Reset x Output Signal On Power-ON Reset Forcibly sets device in halt status. Halt status is released by setting basic timer 0 carry FF RES RESET x Initializes some control registers Initializes program counter, stack, system registers, and some control registers. On Clock Stop Control Operation by Each Reset Signal
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13.3 CE Reset
CE reset is executed when the CE pin goes high. When the CE pin goes high, the RESET signal is output in synchronization with the rising edge of the next basic timer 0 carry FF setting pulse, and the device is reset. When CE reset is executed, the program counter, stack, system registers, and some control registers are initialized by the RESET signal, and the program is started from address 0000H. For the values to which the program counter, stack, system registers, and control registers are to be initialized, refer to the description of each register. The operation of CE reset differs depending on whether the clock stop instruction is used or not. This is described in details in 13.3.1 and 13.3.2 below. 13.3.3 describes points to be noted in executing CE reset. 13.3.1 CE reset when clock stop instruction (STOP s) is not used Figure 13-2 shows the operation. When the clock stop instruction (STOP s) is not used, the basic timer clock select register of the control registers is not initialized. Therefore, after the CE pin has gone high, the RESET signal is output at the rising edge of the basic timer 0 carry FF setting pulse selected at that time (1 ms, 5 ms, 100 ms, or 250 ms), and reset is effected. Figure 13-2. CE Reset Operation When Clock Stop Instruction Is Not Used
5V VDD 0V H CE L H XOUT Basic timer 0 carry FF setting pulse Reset signals IRES L H RES L H RESET L Normal operation Normal operation L H L H
CE reset is executed at the rising edge of the basic timer 0 carry FF setting pulse If basic timer 0 carry FF setting time selected at this time is tSET, the relation between this period "t" and tSET is 0 < t < tSET according to the rising timing of the CE pin. During this period, the program continues operation.
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13.3.2 CE reset when clock stop instruction (STOP s) is used Figure 13-3 shows the operation. When the clock stop instruction is used, the IRES, RES, and RESET signals are output as soon as the "STOP s" instruction has been executed. At this time, the basic timer 0 carry FF setting signal is specified to 100 ms because the basic timer clock select register of the control registers is initialized to 0000B by the RES signal. While the CE pin is low, output of the IRES signal continues, and the device is set in the forced halt status that is released by the basic timer 0 carry. However, the device stops its operation because the clock is stopped. When the CE pin goes high, the clock stop status is released, and oscillation starts. Because the halt status is released by the basic timer 0 carry with the IRES signal at this time, the halt status is released and the program is started from address 0 when the basic timer 0 carry FF setting pulse rises after the CE pin has gone high. Because the basic timer 0 carry FF setting pulse has been initialized to 100 ms, CE reset is executed 50 ms after the CE pin has gone high. Figure 13-3. CE Reset Operation When Clock Stop Instruction Is Used
5V VDD 0V H CE L H XOUT Basic timer 0 carry FF setting pulse Reset signals IRES L H RES L H RESET L Normal operation Clock stop status Halt status 50 ms CE reset Program starts from address 0. L H L H
STOP s instruction
Clock stop released Oscillation started
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13.3.3 Notes on executing CE reset Because CE reset is executed independently of the instruction under execution, remember the following two points (1) and (2): (1) Time required to execute timer processing such as watch When creating a watch program by using the basic timer 0 carry and basic timer 1 interrupt, the processing of the program must be completed within specific time. For details, refer to 11.3.7 Notes on using basic timer 0 carry and 11.4.5 Notes on using basic timer 1 interrupt. (2) Processing of data and flags used for program Care must be exercised in rewriting the contents of data and flags that cannot be processed with one instruction and that must not change in contents even if CE reset is effected, such as security code. Examples of this are given below.
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Example 1. R1 R2 R3 R4 M1 M2 START: Key input processing R1 contents of key A R2 contents of key B SET2 SUB SUB SKT1 BR MAIN: Key input processing R3 contents of key C R4 contents of key D ST ST BR ERROR: Do not operate In the above program, if the security code is "12H", the contents of data memory areas M1 and M2 are "1H" and "2H", respectively. If CE reset is executed at this time, the contents of the key input are compared with security code "12H" in <1>. If they match, the normal processing is performed. If the security code is changed in the main processing, the changed code is written to M1 and M2 in <2> and <3>. If the security code is changed to "34H", therefore, "3H" and "4H" are written to M1 and M2 in <2> and <3>. If CE reset is executed when <2> has been executed, however, the program is started from address 0000H without <3> executed. Therefore, the security code is "32H". This makes it impossible to clear the security system. In this case, use the program shown in Example 2. M2, R4 ;<3> MAIN ; Security code rewriting mode ; Substitutes contents of pressed key for R3 and R4 ; Security code input wait mode ; Substitutes contents of pressed key for R1 and R2 MEM MEM MEM MEM MEM MEM 0.01H 0.02H 0.03H 0.04H 0.11H 0.12H ; First digit of key input data of security code ; Second digit of key input data of security code ; Data of first digit when security code is changed ; Data of second digit when security code is changed ; First digit of current security code ; Second digit of current security code
CMP, Z ;<1> ; Compares security code with input data R1, M1 R2, R2 Z ERROR ; Input data is different from security code
M1, R3 ;<2> ; Rewrites security code
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Example 2. R1 R2 R3 R4 M1 M2 CHANGE START: Key input processing R1 contents of key A R2 contents of key B SKT1 BR ST ST CLR1 SECURITY_CHK: SET2 SUB SUB SKT1 BR MAIN: Key input processing R3 contents of key C R4 contents of key D SET1 ST ST CLR1 BR ERROR: Do not operate In the above program, the CHANGE flag is set to "1" in <5> before the security code is rewritten in <2> and <3>. Even if CE reset is executed before executing <3>, therefore, it is written again in <4>. ; Security code rewriting mode ; Substitutes contents of pressed key for R3 and R4 ; completely changed M1, R3 M2, R4 CHANGE MAIN ;<2> ; Rewrites security code ;<3> ; Resets CHANGE flag to "0" after security code ; has been changed CMP, Z R1, M1 R2, M2 Z ERROR ; Input data is different from security code ;<1> ; Compares security code with input data ; Security code input wait mode ; Substitutes contents of pressed key for R1 and R2 MEM MEM MEM MEM MEM MEM FLG 0.01H 0.02H 0.03H 0.04H 0.11H 0.12H 0.13H.0 ; First digit of key input data of security code ; Second digit of key input data of security code ; Data of first digit when security code is changed ; Data of second digit when security code is changed ; First digit of current security code ; Second digit of current security code ; "1" while security code is changed
CHANGE ;<4> ; If CHANGE flag is "1" SECURITY_CHK M1, R3 M2, R4 CHANGE ; Writes M1 and M2 again
CHANGE ;<5> ; Sets CHANGE flag to "1" until security code is
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13.4 Power-ON Reset
Power-ON reset is executed when the supply voltage VDD of the device rises from a specific level (power-ON clear voltage). If the supply voltage VDD is the same as the power-ON clear voltage or lower, the voltage detection circuit shown in Figure 13-1 outputs a power-ON clear signal (POC). When the power-ON clear signal is output, the crystal oscillation circuit is stopped, and the device operation is stopped. During the output of power-ON clear signal, IRES, RES and RESET signals are output. If the supply voltage VDD exceeds the power-ON clear voltage, the power-ON clear signal is deasserted, and crystal oscillation is started. The IRES, RES, and RESET signals are also deasserted at the same time. At this time, the halt status that is released by the basic timer 0 carry is set by the IRES signal. Therefore, powerON reset is effected at the rising edge of the next basic timer 0 carry FF setting signal. Because the basic timer 0 carry FF setting signal is initialized to 100 ms by the RESET signal, reset is effected 50 ms after the supply voltage VDD has exceeded the power-ON clear voltage, and the program is started from address 0. This operation is illustrated in Figure 13-4. The program counter, stack, system registers, and control registers are initialized as soon as the power-ON clear signal is output. For the values to which the program counter, stack, system registers, and control registers are to be initialized, refer to the description of each register. The power-ON clear voltage is 3.5 V (rated value) during normal operation, and 2.2 V (rated value) in the clock stop status. The power-ON reset operations during normal operation and in the clock stop status are described in 13.4.1 and 13.4.2. 13.4.3 describes the operation when the supply voltage VDD rises from 0 V. Figure 13-4. Power-ON Reset Operation
5V VDD 0V H CE pin L H XOUT pin Basic timer 0 carry FF setting pulse Power-ON clear signal L H IRES L H RES L H RESET L Normal operation
Device operation stopped
Power-ON clear voltage
L H L H
Reset signals
Halt status 50 ms
Power-ON clear released Power-ON reset Oscillation starts Program starts from address 0
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13.4.1 Power-ON reset during normal operation Figure 13-5 (a) shows the operation. As shown in this figure, the power-ON clear signal is output and the device operation is stopped regardless of the input level of the CE pin when the supply voltage VDD drops below 3.5 V. If the supply voltage VDD rises above 3.5 V again, the program is started from address 0000H after a halt status of 50 ms. The normal operation means the operation performed when the clock stop instruction is not used, and includes the halt status set by the halt instruction. 13.4.2 Power-ON reset in clock stop status Figure 13-5 (b) shows the operation. As shown in this figure, the power-ON clear signal is output and the device operation is stopped when the supply voltage VDD drops below 2.2 V. However, it does not seem that the device operation has been changed because the clock stop status is set. When the supply voltage VDD rises to 3.5 V or higher, the program is started from address 0000H after a halt status of 50 ms. 13.4.3 Power-ON reset when supply voltage VDD rises from 0 V Figure 13-5 (c) shows the operation. As shown in this figure, the power-ON clear signal is output before the supply voltage VDD rises from 0 V to 3.5 V. If the supply voltage VDD exceeds the power-ON clear voltage, the crystal oscillation circuit starts operating, and the program is started from address 0000H after a halt status of 50 ms.
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Figure 13-5. Power-ON Reset and Supply Voltage VDD (a) Normal operation (including halt status)
5V 3.5 V VDD 0V H CE L H XOUT L H Power-ON clear signal L Normal operation Device operation stopped Halt status 50 ms Power-ON reset Program starts from address 0 Power-ON clear voltage
Power-ON clear released Oscillation starts
(b) In clock stop status
5V VDD 0V H CE L H XOUT L H Power-ON clear signal L
Normal operation
3.5 V 2.2 V
Power-ON clear voltage
Clock stop
Device operation stopped
Halt status 50 ms Power-ON reset Program starts from address 0
STOP s instruction
Power-ON clear released Oscillation starts
(c) When supply voltage VDD rises from 0 V
5V VDD 0V H CE L H XOUT L H Power-ON clear signal L
Device operation stopped
3.5 V
Power-ON clear voltage
Halt status 50 ms Power-ON reset Power-ON clear Program starts from address 0 released Oscillation starts
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13.5 Relation between CE Reset and Power-ON Reset
On the first application of the supply voltage VDD, power-ON reset and CE reset may be executed simultaneously. The following 13.5.1 through 13.5.3 describe the reset operations performed at this time. 13.5.4 describes the points to be noted when raising the supply voltage VDD. 13.5.1 If VDD and CE pins simultaneously go high Figure 13-6 (a) shows the operation. At this time, the program is started from address 0000H by power-ON reset. 13.5.2 If CE pin goes high in forced halt status set by power-ON reset Figure 13-6 (b) shows the operation. At this time, the program is started from address 0000H by power-ON reset in the same manner as 13.5.1. 13.5.3 If CE pin goes high after power-ON reset Figure 13-6 (c) shows the operation. At this time, the program is started from address 0000H by power-ON reset, and is started again from address 0000H at the rise of the next basic timer 0 carry FF setting signal due to CE reset.
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Figure 13-6. Relation between Power-ON Reset and CE Reset (a) If VDD and CE pins simultaneously go high
5V VDD 0V H CE Basic timer 0 carry FF setting pulse L H L Halt status 50 ms Operation stops 3.5 V Power-ON clear voltage
Normal operation
Power-ON reset Program starts
(b) If CE pin goes high in halt status
5V VDD 0V H CE Basic timer 0 carry FF setting pulse L H L Halt status 50 ms Operation stops 3.5 V Power-ON clear voltage
Normal operation
Power-ON reset Program starts
(c) If CE pin goes high after power-ON reset
5V VDD 0V H CE Basic timer 0 carry FF setting pulse L H L Halt status 50 ms Operation stops 3.5 V Power-ON clear voltage
Normal operation CE reset Program starts
Power-ON reset Program starts
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13.5.4 Notes on raising supply voltage VDD When raising the supply voltage VDD, the following points (1) and (2) must be noted. (1) To raise supply voltage VDD from level below power-ON clear voltage When raising the supply voltage VDD, it must be raised to 3.5 V or higher once. Figure 13-7 illustrates this. As shown in this figure, if a voltage less than 3.5 V is applied on application of VDD in a program, for example, that backs up VDD at 2.2 V by using the clock stop instruction, the power-ON clear signal is continuously output and the program is not executed. At this time, the output ports of the device output undefined values and, in some cases, the current dissipation increases. This means that, if the device is backed up by batteries, the back-up time is substantially shortened. Figure 13-7. Notes on Raising VDD
5V 3.5 V VDD 2.2 V 0V H CE L H XOUT L Basic timer 0 carry FF setting pulse Power-ON clear signal L Operation stops Because output ports are undefined during this period, current dissipation may increase. Halt status 50 ms Operation stops Normal operation
Initializes during this period and then execute clock stop instruction
Power-ON clear voltage
H L H
Back up
Power-ON reset. Program starts.
STOP s instruction
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(2) Releasing clock stop status To restore from the back-up status while the supply voltage VDD is backed up at 2.2 V by using the clock stop instruction, VDD must be raised to 3.5 V or higher within 50 ms after the CE pin has gone high. As shown in Figure 13-8, CE reset is executed to release the clock stop status. Because the power-ON clear voltage is changed to 3.5 V, 50 ms after the CE pin has gone high, power-ON reset is executed unless VDD is 3.5 V or higher at this point. The same applies when lowering VDD. Figure 13-8. Releasing Clock Stop Status
5V 3.5 V VDD 2.2 V 0V H CE L H XOUT L Basic timer 0 carry FF setting pulse Power-ON clear signal L Back up by clock stop instruction Halt status 50 ms Normal operation
Processing when CE = low
Power-ON clear voltage
H L H
Back up
CE reset Program starts Power-ON clear voltage is changed to 3.5 V at this point. Therefore, VDD must be 3.5 V or higher before this point.
STOP s instruction
Because power-ON clear voltage is changed to 2.2 V at this point. Therefore, VDD must not drop to 3.5 V of lower before this point.
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13.6 Power Failure Detection
The power failure detection function is used to identify, when the device has been reset as shown in Figure 139, whether the device has been reset by application of supply voltage VDD or by the CE pin. On power application, the contents of the data memory and output ports are "undefined". These contents are initialized by using the power failure detection function. A power failure is detected in two ways: by detecting the BTM0CY flag using the power failure detection circuit or by detecting the contents of the data memory (RAM judge). The following 13.6.1 and 13.6.2 describe the power failure detection circuit and the method to detect a power failure by using the BTM0CY flag. 13.6.3 and 13.6.4 describe the RAM judge method to detect a power failure. Figure 13-9. Power Failure Detection Flowchart
Program start
Power failure detection Not power failure
Power failure Initializes data memory and output ports
13.6.1 Power failure detection circuit The power failure detection circuit consists of a voltage detection circuit, basic timer 0 carry disable flip-flop that is reset by the output (power-ON clear signal) of the power failure detection circuit, and basic timer 0 carry, as shown in Figure 13-1. The basic timer 0 carry disable FF is set to 1 by the power-ON clear signal, and is reset to 0 when an instruction that reads the BTM0CY flag is executed. When the basic timer 0 carry disable FF is set to 1, the BTM0CY flag is not set to 1. If the power-ON clear signal is output (at power-ON reset), the program is started with the BTM0CY flag reset, and is disabled from being set until an instruction that reads the BTM0CY flag is executed. Once this instruction has been executed, the BTM0CY flag is set each time the basic timer 0 carry FF setting pulse rises. The content of the BTM0CY flag is detected each time the device has been reset. If the flag is reset to 0, powerON reset (power failure) has been executed. If it is set to 1, CE reset (not power failure) has been executed. Because the voltage at which a power failure is detected is the same as the voltage at which power-ON reset is executed, VDD = 3.5 V when the crystal oscillates, and VDD = 2.2 V in the clock stop status. Figure 13-10 shows the transition of the BTM0CY flag status. Figure 13-11 shows the timing chart of Figure 13-10 and operation of the BTM0CY flag.
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Figure 13-10. Status Transition of BTM0CY Flag
CE = Iow <1> CE = don't care VDD = low Operation stops CE = high
<2>
VDD = L 3.5 V Crystal oscillation starts. Forced halt (approx. 50 ms) <3> Power-ON reset CE = L CE = H <6> CE = H L CE = L H CE = L H Normal operation <8> <9> <7> BTM0CY = 0 CE reset Rising of basic timer 0 carry FF setting pulse
BTM0CY flag enabled to be set <4> Clock stop STOP 0 <5>
Normal operation
Normal operation CE reset wait Crystal oscillation starts Forced halt (50 ms)
<10> SKT1 BTM0CY or SKF1 BTM0CY <12> Clock stop <13> STOP 0
<11> SKT1 BTM0CY or SKF1 BTM0CY <15> BTM0CY = 0
Normal operation
<14> CE = H L CE = L H CE = L H
Normal operation <16> <17>
CE reset Rising of basic timer 0 carry FF setting pulse
BTM0CY flag enabled to be set
Normal operation CE reset wait Crystal oscillation starts Forced halt (50 ms)
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Figure 13-11. Operation of BTM0CY Flag (a) If BTM0CY flag is never detected (SKT1 BTM0CY or SKF1 BTM0CY is not executed)
5V VDD 0V H CE Basic timer 0 carry FF setting pluse BTM0CY L Operation in Figure 13-10 <1> <2> <6> <5> <8> <6> <5> <4> <9> <7> STOP s instruction <6> <1> L H L H
<3>
<7> Timer time changed
(b) To detect power failure by using BTM0CY flag
5V VDD 0V H CE Basic timer 0 carry FF setting pluse BTM0CY SKT1 BTM0CY instruction Operation in Figure 13-10 L <1> <2>
<6> <14>
L H L H
<13>
<16>
<14>
<13>
<12>
<17> <15>
<14>
<1>
<3> <15> <11> Timer time changed BTM0CY = 0 Power failure BTM0CY = 1 Not power failure
STOP s instruction BTM0CY = 1 Not power failure
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13.6.2 Notes on detecting power failure with BTM0CY flag The following points must be remembered when counting the watch by using the BTM0CY flag. (1) Updating watch When creating a watch program by using the basic timer 0 carry, the watch must be updated after a power failure has been detected. This is because the BTM0CY flag is reset to 0 for the BTM0CY flag to be read at power failure detection, and consequently, one watch count is missed. (2) Watch updating processing time Updating the watch must be completed until the next basic timer 0 carry FF setting pulse rises. This is because if the CE pin goes high during the watch updating processing, CE reset is executed without the processing completed. For the details of (1) and (2) above, refer to 11.3.7 (b) Adjusting basic timer 0 carry on CE reset. When performing processing on power failure, the following points must be noted. (3) Timing of power failure detection To count the watch by using the BTM0CY flag, it must be carried out since the BTM0CY flag has been read to detect a power failure and the program has been started from address 0000H until the basic timer 0 carry FF setting pulse rises next time. This is because if the basic timer 0 carry FF setting time is set, say, to 5 ms and a power failure is detected 6 ms after the program was started, the BTM0CY flag is skipped once. For more information, refer to 11.3.7 (b) Adjusting basic timer 0 carry on CE reset. As shown in the example below, power failure detection and initialization processing must be performed within the basic timer 0 carry FF setting time. This is because if the CE pin goes high and CE reset is executed during power failure processing and initialization processing, these processing is aborted, and troubles may occur. To change the basic timer 0 carry FF setting time during initialization processing, the instruction that changes the time must be executed at the end of the initialization processing, and the instruction must be one instruction. This is because if the setting time of the basic timer 0 carry FF is changed before initialization processing, the initialization processing may not be completely executed because CE reset may be effected, as shown in the example below.
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Example Program example START: ;<1> Processing on reset ;<2> SKT1 BR BACKUP: ;<3> Updating watch BR INITIAL: ;<4> Initialization processing ;<5> INITFLG BTM0CK1, NOT BTM0CK0 ; Embedded macro ; Sets basic timer 0 carry FF setting time to 5 ms MAIN: Main processing SKT1 BR BR Operation example
5V 0V H L 50 ms 50 ms
; Program address 0000H
BTM0CY INITIAL
; Power failure detection
MAIN
BTM0CY MAIN MAIN
Updating watch
VDD CE
Basic timer 0 carry FF setting pluse
H L <1> <4> <1> <3>
<2> Power failure detection If processing time of <1> + If processing time <1> + <4> is <3> is too long, CE reset longer than 100 ms, CE reset <5> may be effected. may be executed in the middle CE reset CE reset of processing <4.>. Depending on the timing to change the basic timer 0 carry FF setting time, CE reset may be executed immediately. Therefore, if <5> is executed before <4>, power failure processing <4> may not be completely executed.
<2> Power failure detection
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13.6.3 Power failure detection by RAM judge method The RAM judge method detects a power failure by making a judgment whether the contents of the data memory at specified addresses are as specified when the device is reset. An example of a program that detects a power failure by the RAM judge method is shown below. The contents of the data memory are "undefined" on power supply voltage VDD application. A power failure is detected by comparing the "undefined" value with a "specified" value. In some cases, a wrong judgment on power failure detection may be made as described in 13.6.4 Notes on detecting power failure by RAM judge method. The advantage of using the RAM judge method is that a lower supply voltage can be backed up than the level at which the power failure detection circuit detects a power failure, as shown in Table 13-2. Table 13-2. Comparison between Power Failure Detection by Power Failure Detection Circuit and RAM Judge Method
Power Failure Detection Circuit Data retention voltage (at clock stop) Operating status Effective value 1-2 V Rated value 2.2 V Effective value 0-1 V Rated value 2.0 V RAM Judge
No miss-operation
Miss-operation possible
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Example Program that detects power failure by RAM judge method M012 M034 M056 M107 M128 M16F DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 START: SET2 SUB SUB SUB BANK1 SUB SUB SUB BANK0 SKF1 BR ; INITIAL: Initialization processing MOV MOV MOV BANK1 MOV MOV MOV BR BACKUP: Backup processing MAIN: Main processing M107, #DATA3 M128, #DATA4 M16F, #DATA5 MAIN M012, #DATA0 M034, #DATA1 M056, #DATA2 Z BACKUP ; branches to BACKUP when M107, #DATA3 when M128, #DATA4 when M16F, #DATA5 ; M107 = DATA3 and ; M128 = DATA4 and ; M16F = DATA5, CMP, Z When M012, #DATA0 when M034, #DATA1 when M056, #DATA2 ; M012 = DATA0 and ; M034 = DATA1 and ; M056 = DATA2 and MEM MEM MEM MEM MEM MEM DAT DAT DAT DAT DAT DAT 0.12H 0.34H 0.56H 1.07H 1.28H 1.6FH 1010B 0101B 0110B 1001B 1100B 0011B
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13.6.4 Notes on detecting power failure by RAM judge method Because the value of the data memory on application of supply voltage VDD is basically "undefined", the following points (1) and (2) must be noted. (1) Data to be compared Where the number of bits of the data memory to be compared by the RAM judge method is "n", the probability at which the value of the data memory on application of VDD happens to coincide with the value to be compared is (1/2) n. To detect a power failure by the RAM judge method, therefore, back up is judged at a probability of (1/2)n. To reduce this probability, as many bits as possible must be compared. The contents of the data memory on application of VDD are likely to be the same value such as "0000B" and "1111B". Therefore, the data with which the data memory contents are to be compared should be a mix of "0" and "1" such as "1010B" and "0110B" to reduce the possibility of misjudgement. (2) Notes on program As shown in Figure 13-12, if a voltage VDD rises from the level at which destruction of the data memory starts, even if the value of the data memory to be compared is normal, the other portions may be destroyed. At this time, back up is judged by the RAM judge method. It is therefore necessary to take measures to prevent a program hang-up even if the data memory is destroyed. Figure 13-12. VDD and Data Memory Destruction
5V VDD Data memory destruction start voltage 0V
Data memory
Data memory for RAM Judge (normal) Value of data memory not used for RAM Judge may be destroyed.
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14. PLL FREQUENCY SYNTHESIZER
The PLL (Phase Locked Loop) frequency synthesizer is used to lock a frequency in the MF (Medium Frequency), HF (High Frequency), and VHF (Very High Frequency) bands at a specific frequency by means of phase comparison.
14.1 Configuration of PLL Frequency Synthesizer
Figure 14-1 shows the block diagram of the PLL frequency synthesizer. As shown in this figure, the PLL frequency synthesizer consists of an input selector block, a programmable divider (PD), a phase comparator (-DET), a reference frequency generator (RFG), and a charge pump. By connecting these blocks with an external lowpass filter (LPF) and voltage-controlled oscillator (VCO), a PLL frequency synthesizer can be configured. Figure 14-1. Block Diagram of PLL Frequency Synthesizer
Control register
Data buffer Unlock detection block
Input selector block
Programmable divider (PD)
Phase comparator ( -DET)
Charge pump
VCOH VCOL
Reference frequency generator (RFG) Note Voltagecontrolled oscillator (VCO) Lowpass filter (LPF) Note
EO1 EO0
Note
External circuits
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14.2 Functional Outline of PLL Frequency Synthesizer
The PLL frequency synthesizer divides the signal input from the VCOH (pin 32) or VCOL (pin 31) pin by using the programmable divider and outputs a phase difference between the input signal and a reference frequency from the EO1 and EO0 pins. The PLL frequency synthesizer operates only when the CE pin is high. It is disabled when the CE pin is low. For the details of the PLL disabled status, refer to 14.6. The following 14.2.1 through 14.2.5 outline the functions of the each block of the PLL frequency synthesizer. 14.2.1 Input selector block This block selects a pin from which a signal output by an external voltage-controlled oscillator is input. As the input pin, either the VCOH or VCOL pin is selected by the PLL mode select register (PLLMODE: RF address 21H). For the details, refer to 14.3. 14.2.2 Programmable divider The programmable divider divides the signal input from the VCOH or VCOL pin by a ratio set by the program. As the division mode, direct division or pulse swallow mode can be selected by using the PLL mode select register. The division ratio is set by the PLL data register (PLLR: peripheral address 41H) via data buffer. For the details, refer to 14.3. 14.2.3 Reference frequency generator The reference frequency generator generates a reference frequency against which the signal input to the PLL frequency synthesizer is to be compared by the phase comparator. Twelve reference frequencies can be selected by the PLL reference clock select register (PLLRFCLK: RF address 31H). For the details, refer to 14.4. 14.2.4 Phase comparator and unlock detection block The phase comparator compares the division signal output by the programmable divider with the signal from the reference frequency generator and outputs a phase difference between the two signals. The unlock detection block detects the unlock status of the PLL. The unlock status of the PLL is detected by the PLL unlock FF sensibility select register (PLLULSEN: RF address 15H) and PLL unlock FF judge register (PLLULJDG: RF address 05H). For the details, refer to 14.5. 14.2.5 Charge pump The charge pump outputs the signal output by the phase comparator from the EO1 and EO0 pins as a high-level, low-level, or floating output. For the details, refer to 14.5.
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14.3 Input Selector Block and Programmable Divider
14.3.1 Configuration of input selector block and programmable divider Figure 14-2 shows the configuration of the input selector block and programmable divider. As shown in this figure, the input selector block consists of the VCOH and VCOL pins, and the input amplifiers of the respective pins. The programmable divider consists of a 2-modulus prescaler, a swallow counter, a programmable counter, and a division mode selector switch. Figure 14-2. Configuration of Input Selector Block and Programmable Divider
Control register Address Bit b3 P L L M D 3 21H b2 P L L M D 2 b1 P L L M D 1 b0 P L L M D 0 Address Symbol Data buffer (DBF) 0CH DBF3 M S B 16 0DH DBF2 0EH DBF1 0FH DBF0 L S B
Flag symbol
Data
Peripheral address 41H
2-4 decoder
PLL data register 12 bits 4 bits
PSC MF VHF VCOH VHF HF 2-modulus prescaler 1/16, 1/17
12
4
Swallow counter 4 bits VHF HF MF Programmable counter 12 bits fN To -DET
VCOL MF HF PLL disable signal
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14.3.2 Function of input selector block and programmable divider The input selector block and programmable divider selects the input pin and division mode of the PLL frequency synthesizer. As the input pin, the VCOH or VCOL pin can be selected. The voltage of the selected pin is at the intermediate level (about 1/2 VDD). The pin not selected is internally pulled down. Signals are input to these pins via an AC amplifier. Connect a capacitor in series to the pin to cut off the DC component of the input signal. As the division mode, direct division or pulse swallow mode can be selected. The programmable divider divides the input frequency in division mode according to the value set to the swallow counter or programmable counter. Table 14-1 shows the input pins (VCOH and VCOL) and division modes. The input pin and division mode to be used are selected by the PLL mode select register. 14.3.3 describes the configuration and function of the PLL mode select register. The division ratio is set to the programmable divider by the PLL data register via data buffer. 14.3.4 describes the programmable divider and PLL data register. Table 14-1. Input Pins and Division Methods Division Method Direct division (MF) Pulse swallow (HF) Pulse swallow (VHF) VCOH 9 - 150 0.3 256 to 216-1 0100H-FFFFH VCOL 5 - 40 0.3 256 to 216-1 VCOL Pin Used Input Frequency (MHz) 0.5 - 30 Input Amplitude (VP-P) 0.3 16 to 212-1 Division Ratio Set Division Ratio Set to Data Buffer 010xH-FFFxH
(x: lower 4 bits are don't care)
0100H-FFFFH
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14.3.3 Configuration and function of PLL mode select register (PLLMODE) The PLL mode select register sets the division mode of the PLL frequency synthesizer and the pin to be used. The configuration and function of the PLL mode select register are illustrated below. The following paragraphs (1) through (4) outlines the respective division modes.
Flag Symbol Name b3 PLL mode select register (PLLMODE) P L L M D 3 b2 P L L M D 2 b1 P L L M D 1 b0 P L L M D 0 Address
Read/ Write
21H
R/W
Sets division mode of PLL frequency synthesizer 0 0 1 1 0 1 0 1 Disables VCOL and VCOH pins Direct division (VCOL pin MF mode) Pulse swallow (VCOH pin VHF mode) Pulse swallow (VCOL pin HF mode)
Fixed to "0"
On reset
Power-ON Clock stop CE
0
0
0 0
0 0
Retained
(1) Direct division mode (MF) In this mode, the VCOL pin is used. The VCOH pin is pulled down. In the direct division mode, the frequency is divided only by using the programmable counter. (2) Pulse swallow mode (HF) In this mode, the VCOL pin is used. The VCOH pin is pulled down. In the pulse swallow mode, the frequency is divided by using the swallow counter and programmable counter. (3) Pulse swallow mode (VHF) In this mode, the VCOH pin is used. The VCOL pin is pulled down. In the pulse swallow mode, the frequency is divided by using the swallow counter and programmable counter. (4) VCOL and VCOH pin disabled mode In this mode, both the VCOH and VCOL pins are internally pulled down. However, the phase comparator, reference frequency generator, and charge pump operate. Therefore, the operation in this mode is different from that in the PLL disabled status described later.
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14.3.4 Programmable divider and PLL data register The programmable divider divides the signal input from the VCOH or VCOL pin by the value set to the swallow counter or programmable counter. The swallow counter and programmable counter are 4-bit and 12-bit binary down-counters, respectively. A division ratio is set to the swallow counter and programmable counter by the PLL data register (PLLR: peripheral address 41H) via data buffer. Data is set to or read from the PLL data register by using the "PUT PLLR, DBF" or "GET DBF, PLLR" instruction. The division ratio is called "N value". For setting the division ratio (N value) in each division mode, refer to 14.7. (1) PLL data register and data buffer The relation between the PLL data register and data buffer is described next. In the direct division mode, the higher 12 bits of the PLL data register are valid, and all the 16 bits are valid in the pulse swallow mode. In the direct division mode, all the 12 bits of the PLL data register are set to the programmable counter. In the pulse swallow mode, the higher 12 bits are set to the programmable counter, and the lower 4 bits are set to the swallow counter. (2) Relation between division ratio N and divided output frequency of programmable divider The relation between the value "N" set to the PLL data register and the frequency "fN" of the signal divided and output by the programmable divider is as shown below. For details, refer to 14.7. (a) Direct division mode (MF) fIN N (b) Pulse swallow mode (HF, VHF) fIN N
fN =
N: 12 bits
fN =
N: 16 bits
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Name Symbol Address Bit Data b3 DBF3 0CH b2 b1 b0 b3 DBF2 0DH b2 b1
Data Buffer DBF1 0EH b0 b3 b2 b1 b0 b3 DBF0 0FH b2 b1 b0
Transfer data GET can be executed 16 PUT can be executed Peripheral Register
Name PLL data register
b15 b14 b13 b12 b11 b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0 Symbol
Peripheral address
Peripheral hardware PLL frequency synthesizer
Valid data
PLLR
41H
Sets division ratio of PLL frequency synthesizer
0
Don't care Setting prohibited
15 (00FH) 16 (010H) Direct division mode x
Don't care Don't care
Don't care
Division ratio N: N = x
1212 - 1 (FFFH) 0
Don't care
Setting prohibited 255 (00FFH) Pulse swallow mode 256 (0100H)
x
Division ratio N: N = x
1216 - 1 (FFFFH)
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14.4 Reference Frequency Generator
14.4.1 Configuration and function of reference frequency generator Figure 14-3 shows the configuration of the reference frequency generator. As shown in this figure, the reference frequency generator divides 4.5 MHz crystal oscillation to generate the reference frequency "fr" of the PLL frequency synthesizer. Twelve types of reference frequency fr can be selected: 1, 1.25, 2.5, 3, 5, 6.25, 9, 10, 12.5, 25, 50, and 100 kHz. The reference frequency fr is selected by the PLL reference clock select register. The following 14.4.2 describes the configuration and function of the PLL reference clock select register. Figure 14-3. Configuration of Reference Frequency Generator (RFG)
Control register Address Bit b3 P L L R F C K 3 31H b2 P L L R F C K 2 b1 P L L R F C K 1 b0 P L L R F C K 0
Flag symbol
4-16 decoder PLL disable signal Divider 4.5 MHz 1 kHz 1.25 kHz 3 kHz To -DET 50 kHz 100 kHz MUX
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14.4.2 Configuration and function of PLL reference clock select register (PLLRFCLK)
Flag Symbol Name b3 P L L R F C K 3 b2 P L L R F C K 2 b1 P L L R F C K 1 b0 P L L R F C K 0 Address Read/ Write
PLL reference clock select register (PLLRFCLK)
31H
R/W
Sets reference frequency fr of PLL frequency synthesizer 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1.25 kHz 2.5 kHz 5 kHz 10 kHz 6.25 kHz 12.5 kHz 25 kHz 50 kHz 3 kHz Setting prohibited Setting prohibited Setting prohibited 1 kHz 9 kHz 100 kHz PLL disabled
On reset
Power-ON Clock stop CE
1 1
1 1
1 1
1 1
Retained
When the PLL disabled status is selected by the PLL reference clock select register, the VCOH and VCOL pins are internally pulled down. The EO1 and EO0 pins are floated. For the details of the PLL disabled status, refer to 14.6.
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14.5 Phase Comparator (-DET), Charge Pump, and Unlock Detection Block
14.5.1 Configuration of phase comparator, charge pump, and unlock detection block Figure 14-4 shows the configuration of the phase comparator, charge pump, and unlock detection block. The phase comparator compares the phase of the divided frequency "fN" output by the programmable divider with that of the reference frequency "fr" output by the reference frequency generator, and outputs an up request signal (UP) and down request signal (DW). The charge pump outputs the signal output by the phase comparator from the error out pins (EO1 and EO0 pins). The unlock detection block consists of a sensibility select circuit and an unlock FF, and detects the unlock status of the PLL frequency synthesizer. The following 14.5.2, 14.5.3, and 14.5.4 respectively describe the operations of the phase comparator, charge pump, and unlock detection block. Figure 14-4. Configuration of Phase Comparator, Charge Pump, and Unlock Detection Block
Control register Address 15H 05H b3 b2 b1 b0 b3 b2 b1 b0 Bit
P L U Flag L symbol S E N 3 Phase comparator ( -DET) fr UP
P L U L S E N 2
P L U L S E N 1
P L U L S000 E N 0
P L L U L
Unlock detection block
Reference frequency generator
Sensibility select
Unlock FF
Charge pump VDD P-ch EO1 N-ch VDD Programmable divider fN DW P-ch EO0 N-ch
PLL disable signal
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14.5.2 Function of phase comparator As shown in Figure 14-4, the phase comparator compares the phase of the divided frequency "fN" output by the programmable divider with the phase of the reference frequency "fr" and outputs an up request or a down request signal. If the divided frequency fN is lower than the reference frequency fr, it outputs an up request signal; if fN is higher than fr, it outputs a down signal. Figure 14-5 shows the relations among reference frequency fr, divided frequency fN, up request signal, and down request signal. In the PLL disabled status, neither the up nor down request signal is output. The up and down request signals are input to the charge pump and unlock detection block. Figure 14-5. Relation among fr, fN, and UP and DW Signals (a) If fN lags behind fr in phase
fr fN UP DW
(b) If fN advances fr in phase
fr fN UP DW
(c) If fN and fr are in the same phase
fr fN UP DW
(d) If fN is lower than fr
fr fN UP DW
14.5.3 Charge pump As shown in Figure 14-4, the charge pump outputs the up or down request signal from the phase comparator, from to the error out pins (EO1 and EO0 pins). Therefore, the relation among the output of the error out pins, divided frequency fN, and reference frequency fr is as follows: When reference frequency fr > divided frequency fN: low level output When reference frequency fr < divided frequency fN: high level output When reference frequency fr = divided frequency fN: floating
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14.5.4 Unlock detection block As shown in Figure 14-4, the unlock detection block detects the unlock status of the PLL frequency synthesizer from the up request or down request signal of the phase comparator. In the unlock status, either the up request or down request signal outputs low level, and the unlock status is detected by this low-level signal. In the unlock status, the unlock flip-flop (FF) is set to 1. The status of the unlock FF is detected by the PLL unlock FF judge register (refer to 14.5.5). The unlock FF is set at the cycle of reference frequency fr selected at that time. It is reset when the contents of the PLL unlock FF judge register are read by using the PEEK instruction (Read & Reset). Therefore, the unlock FF must be detected in a cycle longer than the cycle 1/fr of the reference frequency fr. The unlock sensibility select circuit controls the status in which the unlock FF is set by delaying the up request or down request signal of the phase comparator. If the signal is delayed for the longer time, the unlock FF is not set even if there is a large phase difference between the divided frequency fN and reference frequency fr. The delay time of the unlock sensibility select circuit is set by the PLL unlock FF sensibility select register (refer to 14.5.6). 14.5.5 Configuration and function of PLL unlock FF judge register (PLLULJDG)
Flag Symbol Name b3 PLL unlock FF Judge register (PLLULJDG) b2 b1 b0 P L L U L Address
Read/ Write
0
0
0
05H
R & Reset
Detects status of unlock FF 0 1 Unlock FF = 0: PLL Iock status Unlock FF = 1: PLL unlock status
Fixed to "0"
On reset
Power-ON Clock stop CE
0
0
0
Undefined Retained Retained
This register is a read-only register, and is reset when its contents are read to the window register by the "PEEK" instruction. Because the unlock FF is set in the cycle of the reference frequency fr, the contents of this register must be read to the window register in a cycle longer than reference frequency cycle 1/fr.
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14.5.6 Configuration and function of PLL unlock FF sensibility select register (PLULSEN)
Flag Symbol Name b3 P L U L S E N 3 b2 P L U L S E N 2 b1 P L U L S E N 1 b0 P L U L S E N 0 Address
Read/ Write
PLL unlock FF sensibility select register (PLULSEN)
15H
R/W
Sets delay time between reference frequency fr and divided frequency fN necessary for setting unlock FF 0 0 1 1 0 1 0 1 0.9 to 1.0 s or longer 1.9 to 2.0 s or longer 0.45 to 0.55 s or longer Unlock FF disable (always PLLUL = 1)
Fixed to "0"
On reset
Power-ON Clock stop CE
0
0
0 0
0 0
Retained
When the unlock FF disable status is set, the unlock FF is always set. If the lock status of the PLL is detected by the PLL unlock FF judge register, it is always in the unlock status (PLLUL flag = 1).
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14.6 PLL Disabled Status
The PLL frequency synthesizer stops operating (disabled) while the CE pin (pin 13) is low. It also stops when the PLL disabled status is selected by the PLL reference mode select register. Table 14-2 shows the operations of the respective blocks in the PLL disabled status. When the VCOL and VCOH pins are disabled by the PLL mode select register, only the VCOL and VCOH pins are internally pulled down, and the other blocks operate. The PLL reference mode select register and PLL mode select register are not initialized (retain the previous status) at CE reset. Therefore, when the CE pin goes high after the CE pin has gone low once and the PLL has been disabled, these registers return to the previous status. If it is necessary to disable the PLL at CE reset, initialize the PLL by program. The PLL is disabled at power-ON reset. Table 14-2. Operations of Respective Block in PLL Disabled Status
Condition
CE Pin = Low Level (PLL Disabled)
CE Pin = High Level PLLRFCLK = 1111B (PLL disabled) PLLMODE = 0000B (VCOH and VCOL disabled) Internally pulled down
Block VCOL and VCOH pins Programmable counter Reference frequency generator Phase comparator Charge pump Error out pins floated Output stopped Output stopped Division stopped Internally pulled down
Internally pulled down
Division stopped
Operates
Output stopped
Operates
Output stopped
Operates
Error out pins floated
Operates, but normally outputs low level because no signal is input
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14.7 Using PLL Frequency Synthesizer
To control the PLL frequency synthesizer, the following data is necessary: (1) Division mode (2) Pins used (4) Division ratio : direct division (MF), pulse swallow (HF, VHF) : VCOL or VCOH pin :N
(3) Reference frequency : fr
The following 14.7.1 through 14.7.3 describe how to set the PLL data in the respective division modes (MF, HF, and VHF). 14.7.1 Direct division mode (1) Selecting division mode Select the direct division mode by the PLL mode select register. (2) Pins used When the direct division mode is selected, the VCOL pin is enabled to operate. (3) Setting reference frequency fr Set a reference frequency by using the PLL reference clock select register. (4) Calculating division ratio N Calculate as follows: fVCOL fr where, fVCOL fr (5) Example of setting PLL data Setting the data to receive the broadcasting in the following MW band is described. Reception frequency Reference frequency Division ratio N is 1422 + 450 fVCOL = 9 fr : : 1422 kHz (MW band) 9 kHz +450 kHz : input frequency of VCOL pin : reference frequency
N=
Intermediate frequency :
N=
= 208 (decimal) = 0D0H (hexadecimal)
Set data to the PLL data register (PLLR: peripheral address 41H), PLL mode select register (PLLMODE: RF address 21H), and PLL reference clock select register (PLLRFCLK: RF address 31H) as follows:
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PLLR 0000 0 1101 D 0000 0 Don't care
PLLMODE PLLRFCLK 0001 MF 1101 9kHz
14.7.2 Pulse swallow mode (HF) (1) Selecting division mode Select the pulse swallow mode by the PLL mode select register. (2) Pins used When the pulse swallow mode is selected, the VCOL pin is enabled to operate. (3) Setting reference frequency fr Set a reference frequency by using the PLL reference clock select register. (4) Calculating division ratio N Calculate as follows: fVCOL fr where, fVCOL fr (5) Example of setting PLL data Setting the data to receive the broadcasting in the following SW band is described. Reception frequency Reference frequency Division ratio N is 25500 + 450 fVCOL = = 5190 (decimal) fr 5 = 1446H (hexadecimal) : : 25.50 MHz (SW band) 5 kHz +450 kHz : input frequency of VCOL pin : reference frequency
N=
Intermediate frequency :
N=
Set data to the PLL data register (PLLR: peripheral address 41H), PLL mode select register (PLLMODE: RF address 21H), and PLL reference clock select register (PLLRFCLK: RF address 31H) as follows:
PLLR 0001 1 0100 4 0100 4 0110 6 PLLMODE PLLRFCLK 0011 MF 0010 5 kHz
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14.7.3 Pulse swallow mode (VHF) (1) Selecting division mode Select the pulse swallow mode by the PLL mode select register. (2) Pins used When the pulse swallow mode is selected, the VCOH pin is enabled to operate. (3) Setting reference frequency fr Set a reference frequency by using the PLL reference clock select register. (4) Calculating division ratio N Calculate as follows: fVCOH fr where, fVCOH : input frequency of VCOH pin fr (5) Example of setting PLL data Setting the data to receive the broadcasting in the following FM band is described. Reception frequency Reference frequency Division ratio N is 100.0 + 10.7 fVCOH = = 4428 (decimal) fr 0.025 = 114CH (hexadecimal) : : 100.0 MHz (FM band) 25 kHz +10.7 MHz : reference frequency
N=
Intermediate frequency :
N=
Set data to the PLL data register (PLLR: peripheral address 41H), PLL mode select register (PLLMODE: RF address 21H), and PLL reference clock select register (PLLRFCLK: RF address 31H) as follows:
PLLR 0001 1 0001 1 0100 4 1100 C PLLMODE PLLRFCLK 0010 VHF 0110 25 kHz
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14.8 Status on Reset
14.8.1 On power-ON reset The PLL is disabled because the PLL reference clock select register is initialized to 1111B. 14.8.2 On execution of clock stop instruction The PLL is disabled when the CE pin goes low. 14.8.3 On CE reset (1) CE reset after execution of clock stop instruction The PLL is disabled because the PLL reference clock select register is initialized to 1111B by the clock stop instruction. (2) CE reset without clock stop instruction executed The PLL reference clock select register restores the previous status when the CE pin goes high because the register holds the previous status. 14.8.4 In halt status The set status is retained as long as the CE pin is high.
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15. GENERAL-PURPOSE PORTS
The general-purpose ports output high-level, low-level, and floating signals to external circuits, and read high-level and low-level signals from the external circuits.
15.1 Configuration and Classification of General-Purpose Ports
Figure 15-1 shows the block diagram of the general-purpose ports. Table 15-1 classifies the general-purpose ports. As shown in Figure 15-1, the general-purpose ports include port 0A (P0A) through port 2A (P2A) that set data from addresses 70H through 73H (port registers) of each bank of the data memory, ports 0E (P0E), 0F (P0F), and 0X (P0X) that set data from addresses 68H, 69H, 6BH, and 6DH of bank 0 of the data memory, and ports 0Y (P0Y) and 0X (P0X) that set data via data buffer (DBF) (data can be set to P0X via port register and peripheral register). Each port consists of general-purpose port pins (for example, P0A3 to P0A0 pins for port 0A). The general-purpose ports are classified into I/O ports, input ports, and output ports, as shown in Table 15-1. The I/O ports are further subdivided into bit I/O ports which can be specified in the input or output mode in 1-bit (1-pin) units, and a group I/O ports which can be specified in the input or output mode in 4-bit (4-pin) units.
200
Figure 15-1. Block Diagram of General-Purpose Ports
0 0 1 2 3 4 5 6 7
1
2
3
4
5
Column address 6789
A
B
C
D
E
F Peripheral address 0CH 42H
DBF Data memory Port register BANK0 68 69 6B BANK1 BANK2 BANK3 System register
Bit l/O Bit Group l/O l/O In
Row address
6D
Bit l/O Out Out In
Out
Setting of data
Out Out Out Out
P 0 A
P 0 B
P 0 C
P 0 D
P 1 A
P 1 B
P 1 C
P 1 D
P 2 A
-
-
-
-
-
-
- Control register
P 0 E
P 0 F
P 0 X
P 0 Y
Setting of I/O mode Example of pin configuration of P0A P 0 A 3 p i n P 0 A 2 p i n P 0 A 1 p i n P 0 A 0 p i n
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Table 15-1. Classification of General-Purpose Ports Classification Generalpurpose ports Group I/O Input port I/O ports Bit I/O Port Port 0A Port 0B Port 1A Port 0C Port 0D Port 1D Output port Port 1B Port 1C Port 2A Port 0E Port 0F Port 0X Port 0Y Peripheral register Port register (shared with LCD segment register) Port register Port register Port register Data Set by: Port register
15.2 Functional Outline of General-Purpose Ports
A general-purpose output port or a general-purpose I/O port set in the output mode outputs a high or low level from the corresponding pin when data is set to the port register or port group register. A general-purpose input port or a general-purpose I/O port set in the input mode detects the input signal level applied to the corresponding pin by reading the contents of the port register. A general-purpose I/O port can be set in the input or output mode by using the corresponding control register. In other words, the input or output mode can be changed by program. P0A through P0D, P1A through P1D, and P2A are set as general-purpose ports at power-ON reset. The mode of the pins multiplexed with the other hardware is independently set by the corresponding control register. P0E, P0F, P0X, and P0Y are set as LCD segment signal output pins at power-ON reset. These ports can be independently specified as general-purpose output ports by using the corresponding control register. The following 15.2.1 through 15.2.5 describe the functions of the port register, port group register, and the functional outline of the respective ports.
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15.2.1 General-purpose port data registers (port registers) A port register sets the output data of the corresponding general-purpose port or reads the input data of the port. Since the port register is located on the data memory, it can be operated by all the data memory manipulation instructions. Figure 15-2 shows the relation between each port register and the corresponding pin. The output data of each port pin is set by setting the data to the port register corresponding to the pin set as a general-purpose output port. The input status of each port pin is detected by reading the port register corresponding to the port set as a generalpurpose input port. Table 15-2 shows the relation between each port (pin) and port register. Figure 15-2. Relation between Port Register and Pin
Port Register Bank Address Bit P P P P
3 2 1 0
n m b3 b2 b1 b0
Significance of bit of port register Address of port register (e.g., 70H = A, 71H = B, 72H = C, 73H = D) Bank of port register "P" or Port
Reserved words are defined by the assembler (AS17K) for port registers. Because these reserved words are defined in flag (bit) units, assembler embedded macro instructions can be used. Note that no reserved word of data memory type is defined for the port register. P0E, P0F, P0X, and P0Y are shared by LCD segment signal output pins. The port registers of P0E, P0F, and P0X are also shared by LCD segment registers. Because the LCD segment registers are also located on the data memory, they can be used in the same manner as the port registers. 15.2.2 Port 0X (P0X) and port 0Y (P0Y) group registers The port 0X (P0X) group register sets the output data of P0X. This register is shared by an LCD group register, and is allocated to peripheral address 0CH. The port 0Y (P0Y) group register sets the output data of P0Y. This register is shared by a key source data register, and is allocated to peripheral address 42H. For details, refer to 15.6.7.
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15.2.3. General-purpose I/O ports (P0A, P0B, P0C, and P1A) P0A, P0B, P0C, and P1A are set in the input or output mode by the P0A bit I/O select register (P0ABIO: RF address 37H), P0B bit I/O select register (P0BBIO: RF address 36H), P0C group I/O select register (P0CBIO: RF address 27H), and P1A bit I/O select register (P1ABIO: RF address 35H), respectively. The input/output data of the P0A, P0B, P0C, and P1A are set by port registers P0A (address 70H of BANK0), P0B (address 71H of BANK0), P0C (address 72H of BANK0), and P1A (address 70H of BANK1), respectively. Refer to Table 15-2. For details, refer to 15.3. 15.2.4 General-purpose input ports (P0D and P1D) The input data of P0D and P1D are read by using port registers P0D (address 73H of BANK0) and P1D (address 73H of BANK1), respectively. Refer to Table 15-2. For details, refer to 15.4. 15.2.5 General-purpose output ports (P1B, P1C, P2A, P0E, P0F, P0X, and P0Y) (1) P1B, P1C, and P2A The output data of P1B, P1C, and P2A are set by using port registers P1B (address 71H of BANK1), P1C (address 72H of BANK1), and P2A (address 70H of BANK2), respectively. Refer to Table 15-2. For details, refer to 15.5. (2) P0E, P0F, P0X, and P0Y P0E, P0F, P0X, and P0Y usually operates as LCD segment signal output pins. These ports are used as output ports if so specified by the LCD port select register (LCDPORT: RF address 11H). The output data of P0E and P0F are set by the P0E register (shared by LCD segment register LCDD13, address 6DH of BANK0) and P0F register (shared with LCDD11, address 6BH of BANK0). The output data of P0X is set by the P0XL register (shared by LCDD8, address 68H of BANK0) and P0XH (shared by LCDD11, address 69H of BANK0), or by the port 0X (P0X) group register via data buffer. The output data of P0Y is set by the port 0Y (P0Y) group register via data buffer. Refer to Table 15-2. For details, refer to 15.6.
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Table 15-2. Relation between Port Pins and Port Registers (1/2)
Port Number Pin Symbol I/O Bank Data Setting Method Port register (Data Memory) Address Symbol Bit Symbol (Reserved Word) Port 0A (P0A) Remark
----------------------4 P0A2 ----------------------5 P0A1 ----------------------6 P0A0 P0B3
3
P0A3
I/O (bit I/O)
BANK0
70H
P0A
----------------------b2 P0A2 ----------------------b1 P0A1 ----------------------b0 P0A0 P0B3
b3
P0A3
Port 0B (P0B)
----------------------8 P0B2 ----------------------9 P0B1 ----------------------10 79 P0B0
7
I/O (bit I/O)
71H
P0B
----------------------b2 P0B2 ----------------------b1 P0B1 ----------------------b0 b3 P0B0
b3
Port 0C (P0C)
----------------------80 P0C2 ----------------------1 P0C1 ----------------------2 P0C0
P0C3
I/O (group I/O)
72H
P0C
----------------------b2 P0C2 ----------------------b1 P0C1 ----------------------b0 P0C0 P0D3
P0C3
Port 0D (P0D)
----------------------76 P0D2 ----------------------77 P0D1 ----------------------78 P0D0 P1A3
75
P0D3
Input
73H
P0D
----------------------b2 P0D2 ----------------------b1 P0D1 ----------------------b0 P0D0 P1A3
b3
Port 1A (P1A)
----------------------15 P1A2 ----------------------16 P1A1 ----------------------17 P1A0 P1B3
14
I/O (bit I/O)
BANK1
70H
P1A
----------------------b2 P1A2 ----------------------b1 P1A1 ----------------------b0 b3 P1A0 P1B3
b3
Port 1B (P1B)
----------------------19 P1B2 ----------------------20 P1B1 ----------------------21 22 P1B0
18
Output
71H
P1B
----------------------b2 P1B2 ----------------------b1 P1B1 ----------------------b0 P1B0
Port 1C (P1C)
----------------------23 P1C2 ----------------------24 P1C1 ----------------------25 P1C0 P1D3
P1C3
Output
72H
P1C
----------------------b2 P1C2 ----------------------b1 P1C1 ----------------------b0 P1C0 P1D3
b3
P1C3
Port 1D (P1D)
----------------------27 P1D2 ----------------------28 P1D1 ----------------------29 P1D0 No pins
26
Input
73H
P1D
----------------------b2 P1D2 ----------------------b1 P1D1 ----------------------b0 P1D0 P2A3
b3
Port 2A (P2A)
BANK2
70H
P2A
-------------------------------------42 P2A0 Output 71H ---
----------------------b2 P2A2 Cannot be used as data memory. ----------------------b1 P2A1 -------------------------------------------------------------b0 P2A0 --b3 b2 b1 b0 Nothing is allocated. Cannot be used as data memory.
b3
Nothing is allocated.
72H
---
b3 b2 b1 b0
---
73H
---
b3 b2 b1 b0
---
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Table 15-2. Relation between Port Pins and Port Registers (2/2)
Port Number Pin Symbol I/O Bank Data Setting Method Port register (Data Memory) Address Symbol Bit Symbol (Reserved Word) BANK3 70H --b3 b2 b1 b0 71H --b3 b2 b1 b0 72H --b3 b2 b1 b0 73H --b3 b2 b1 b0 Port 0E (P0E) --------P0X, P0Y Group Registers (Peripheral Registers) Peripheral Symbol (ReAddress served Word) Nothing is allocated. Cannot be used as data memory. Bit
----------------------50 P0E2 ----------------------51 P0E1 ----------------------52 P0E0 P0F3
49
P0E3
Output
Bank1
6BH
P0E
(Shared by LCDD11)
----------------------b2 P0E2 ----------------------b1 P0E1 ----------------------b0 b3 P0E0 P0F3
b3
P0E3
Port 0F (P0F)
----------------------46 P0F2 ----------------------47 P0F1 ----------------------48 P0F0
45
Output
6DH
P0F
(Shared by LCDD13)
----------------------b2 P0F2 ----------------------b1 P0F1 ----------------------b0 b3 P0F0
Port 0X (P0X)
----------------------54 P0X4 ----------------------55 P0X3 ----------------------56 57 P0X2 P0X1
53
P0X5
Output
69H
P0XH
(Shared by LCDD9)
----------------------b2 P0XH2 ----------------------b1 P0XH1 ----------------------b0 b3 P0XH0 P0XL3
P0XH3
0CH
P0X
(Shared by LCDR4)
----------------------58 P0X0 --------------------------------------No pins
68H
P0XL
(Shared by LCDD8)
----------------------b2 P0XL2 ----------------------b1 P0XL1 ----------------------b0 P0XL0 42H P0Y
-----------b6 -----------b5 -----------b4 -----------b3 -----------b2 -----------Don't care
b7
Port 0Y (P0Y)
----------------------60 P0Y14 ----------------------61 | 72 P0Y13 | P0Y2
59
P0Y15
Output
(Shared by KSR)
-----------b14 -----------b13 | b2
b15
----------------------73 P0Y1 ----------------------74 P0Y0
-----------b1 -----------b0
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15.3 General-Purpose I/O Ports (P0A, P0B, P0C, and P1A)
15.3.1 Configuration of I/O ports (1) through (4) below show the configuration of the I/O ports. (1) P0A (P0A0 pin), P0B (P0B1 pin), P1A (P1A3, P1A2, P1A1, and P1A0 pins)
VDD I/O select flag
Output latch
Write instruction
Port register (1 bit) VDD
1 0
Read instruction
RESET
(2) P0A (P0A1 pin) P0B (P0B3, P0B2, and P0B0 pins)
I/O select flag
VDD
Output latch
Write instruction
Port register (1 bit) VDD
1 0
Read instruction
RESET
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(3) P0C (P0C3, P0C2, P0C1, and P0C0 pins)
VDD I/O select flag
Output latch
Write instruction
Port register (1 bit) VDD
1 0
Read instruction
(4) P0A (P0A3, and P0A2 pins)
I/O select flag
Output latch
Write instruction
Port register (1 bit) VDD
Read instruction
RESET
15.3.2 Using I/O ports The I/O ports are set in the input or output mode by the control register P0A, P0B, P0C, and the I/O select registers of P1A, respectively. The bit I/O ports (P0A, P0B, and P1A) can be set in the input or output mode in 1-bit units, and the group I/O port (P0C) can be set in the input or output mode in 4-bit units. To set the output data or to read the input data, execute an instruction that writes data to the corresponding port register or that reads data from the corresponding port register. The following 15.3.3 describes the I/O select register of each port. 15.3.4 and 15.3.5 describe the input and output modes of the I/O ports. 15.3.6 describes the points to be noted in using the I/O ports.
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15.3.3 Port 0A bit I/O select register (P0ABIO) Port 0B bit I/O select register (P0BBIO) Port 1A bit I/O select register (P1ABIO) Port 0C group I/O select register (P0CGPIO) Port 0A bit I/O, port 0B bit I/O, port 1A bit I/O, and port 0C group I/O select registers sets the input or output mode of each pin of P0A, P0B, P1A, and P0C. (1) through (4) shows the configuration and functions of these registers. (1) Port 0A bit I/O select register (P0ABIO)
Flag Symbol Name b3 P 0 Port 0A bit l/O select register (P0ABIO) A B I O 3 b2 P 0 A B I O 2 b1 P 0 A B I O 1 b0 P 0 A B I O 0 37H R/W Address Read/ Write
Sets input/output mode 0 1 Sets P0A0 pin in input mode Sets P0A0 pin in output mode
Sets input/output mode 0 1 Sets P0A1 pin in input mode Sets P0A1 pin in output mode
Sets input/output mode 0 1 Sets P0A2 pin in input mode Sets P0A2 pin in output mode
Sets input/output mode 0 1 Sets P0A3 pin in input mode Sets P0A3 pin in output mode
On reset
Power-ON Clock stop CE
0 0 0
0 0 0
0 0 0
0 0 0
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(2) Port 0B bit I/O select register (P0BBIO)
Flag Symbol Name b3 P 0 Port 0B bit l/O select register (P0BBIO) B B I O 3 b2 P 0 B B I O 2 b1 P 0 B B I O 1 b0 P 0 B B I O 0 36H Address
Read/ Write
R/W
Sets input/output mode 0 1 Sets P0B0 pin in input mode Sets P0B0 pin in output mode
Sets input/output mode 0 1 Sets P0B1 pin in input mode Sets P0B1 pin in output mode
Sets input/output mode 0 1 Sets P0B2 pin in input mode Sets P0B2 pin in output mode
Sets input/output mode 0 1 Sets P0B3 pin in input mode Sets P0B3 pin in output mode
On reset
Power-ON Clock stop CE
0 0 0
0 0 0
0 0 0
0 0 0
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(3) Port 1A bit I/O select register (P1ABIO)
Flag Symbol Name b3 P 1 Port 1A bit l/O select register (P1ABIO) A B I O 3 b2 P 1 A B I O 2 b1 P 1 A B I O 1 b0 P 1 A B I O 0 35H R/W Address Read/ Write
Sets input/output mode 0 1 Sets P1A0 pin in input mode Sets P1A0 pin in output mode
Sets input/output mode 0 1 Sets P1A1 pin in input mode Sets P1A1 pin in output mode
Sets input/output mode 0 1 Sets P1A2 pin in input mode Sets P1A2 pin in output mode
Sets input/output mode 0 1 Sets P1A3 pin in input mode Sets P1A3 pin in output mode
On reset
Power-ON Clock stop CE
0 0 0
0 0 0
0 0 0
0 0 0
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(4) Port 0C group I/O select register (P0CGPIO)
Flag Symbol Name b3 b2 b1 b0 P 0 Port 0C group l/O select register (P0CGPIO) 0 0 0 C G I O 27H R/W Address Read/ Write
Sets input/output mode 0 1 Sets P0C3-P0C0 pins in input mode Sets P0C3-P0C0 pins in output mode
Fixed to "0"
On reset
Power-ON Clock stop CE
0
0
0
0 0 0
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15.3.4 To use I/O ports (P0A, P0B, P0C, or P1A) as input port The pin to be set in the input mode is selected by the I/O select register of each port. Note that P0C can be set in the input or output mode in 4-bit units only. The pin set in the input mode is floated (Hi-Z) and waits for input of an external signal. To read the input data of a pin, execute an instruction that reads the contents of the port register corresponding to the pin, such as "SKT" instruction. When a high level is input to each pin, "1" is read to the port register; when a low level is input, "0" is read to the register. If an instruction that writes the port register of the port set in the input mode, such as "MOV" instruction, is executed, the contents of the output latch are rewritten. 15.3.5 To use I/O ports (P0A, P0B, P0C, or P1A) as output port The pin to be set in the output mode is selected by the I/O select register of each port. Note that P0C can be set in the input or output mode in 4-bit units only. The pin set in the output mode outputs the contents of the output latch from each pin. To set the output data, execute an instruction that writes data to the port register corresponding to the pin, such as "MOV" instruction. To output a high level to each pin, write "1" to the corresponding port register. To output a low level, write "0" to the register. A port pin can be floated by setting it in the input mode. When an instruction that reads the port register set in the output mode, such as "SKT" instruction, is executed, the contents of the output latch are read. Note, however, that the status of the P0A3 and P0A2 pins are read as is, the contents of the output latch and read data may differ. For further information, refer to 15.3.6.
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15.3.6 Notes on using I/O ports (P0A3 and P0A2 pins) When using the P0A3 and P0A2 pins as output pins as shown in the example below, the contents of the output latch may be rewritten. Example To specify P0A3 and P0A2 pins as output port pins INITFLG P0ABIO3, P0ABIO2, NOT P0ABIO1, NOT P0ABIO0 ; Sets P0A3 and P0A2 pins in output mode INITFLG P0A3, P0A2, NOT P0A1, NOT P0A0 ; Outputs high level to P0A3 and P0A2 pins ; <1> CLR1 P0A3 ; Outputs low level to P0A3 pin Macro expansion AND . MF. P0A3 SHR 4, #. DF. (NOT P0A3 AND 0FH)
If the P0A2 pin happens to be made low externally when the instruction <1> in the above example is executed, the contents of the output latch of the P0A2 pin are written to "0" by the "CLR1" instruction. In other words, if an operation instruction (such as "ADD" or "OR") is executed to the P0A port register when the P0A3 or P0A2 pin is set in the output mode, the contents of the output latch are written to the pin level at that time, regardless of the previous status. 15.3.7 Reset status of I/O ports (P0A, P0B, P0C, and P1A) (1) On power-ON reset All the I/O ports are set in the input mode. The contents of the output latch are "undefined"; therefore, the output latch must be initialized by program as necessary when setting the ports in the output mode. (2) On CE reset All the I/O ports are set in the input mode. The contents of the output latch are retained. (3) On execution of clock stop instruction All the I/O ports are set in the input mode. The contents of the output latch are retained. The I/O ports, except P0C, prevent an increase in the current dissipation due to noise superimposed on the input buffer, by using the RESET signal output, as described in 15.3.1, when the clock stop instruction is executed. P0C must be externally pulled down or up as necessary because, if it is floated when the clock stop instruction is executed, its current dissipation may increase due to external noise. (4) In halt status The I/O ports retain the previous status.
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15.4 General-Purpose Input Ports (P0D and P1D)
15.4.1 Configuration of input ports (1) and (2) below show the configuration of the input ports. (1) P0D (P0D3, P0D2, P0D1, and P0D0 pins)
To A/D converter Write instruction VDD Port register (1 bit)
Input latch
Read instruction
High ON resistance
ADC select signal Key source signal timing output RESET
(2) P1D (P1D3, P1D2, P1D1, and P1D0 pins)
To frequency counter or A/D converter Write instruction VDD Port register (1 bit)
Read instruction
RESET
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15.4.2 Example of using input ports (P0D and P1D) The input data is read by executing an instruction that reads the contents of the port register corresponding to each pin, such as "SKT" instruction. When a high level is input to the pin, "1" is read to the port register; when a low level is input, "0" is read to the register. The contents of the port register are not changed by executing a write instruction, such as "MOV". 15.4.3 Notes on using input port (P0D) P0D is internally pulled down when used as a general-purpose port. 15.4.4 Reset status of input ports (P0D and P1D) (1) On power-ON reset All the input ports are specified as general-purpose input ports. (2) On CE reset All the input ports are specified as general-purpose input ports. (3) On execution of clock stop instruction All the input ports are specified as general-purpose input ports. P1D prevents an increase in the current dissipation due to noise superimposed on the input buffer as described in 15.4.1 because the RESET signal is output when the clock stop instruction is executed. P0D is internally pulled down. (4) In halt status The input ports retain the previous status.
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15.5 General-Purpose Output Ports (P1B, P1C, and P2A)
15.5.1 Configuration of output ports (P1B, P1C, and P2A) (1) and (2) below show the configuration of the output ports. (1) P1B (P1B0 pin) P1C (P1C3, P1C2, P1C1, and P1C0 pins) P2A (P2A0 pin)
VDD Output latch Write instruction
Port register (1 bit)
Read instruction
(2) P1B (P1B3, P1B2, and P1B1 pins)
Output latch
Write instruction
Port register (1 bit)
Read instruction
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15.5.2 Example of using output ports (P1B, P1C, and P2A) The output ports output the contents of the output latch from each pin. The output data is set by executing an instruction that writes data to the port register corresponding to each pin, such as "MOV" instruction. Write "1" to the port register to output a high level to the port pin; write "0" to the register to output a low level. Note, that the P1B3, P1B2, and P1B1 pins float when they output a high level, because they are open-drain output ports. When an instruction that reads the port register, such as "SKT" instruction, is executed, the contents of the output latch are read. 15.5.3 Reset status of output ports (P1B, P1C, and P2A) (1) On power-ON reset The contents of the output latch are output. Because the contents of the output latch are "undefined", an "undefined" value is output for a fixed period (until the output latch is initialized by program). (2) On CE reset The contents of the output latch are output. Because the contents of the output latch are retained, the output data is not affected by CE reset. (3) On execution of clock stop instruction The contents of the output latch are output. Because the contents of the output latch are retained, the output data is not affected by execution of the clock stop instruction. Therefore, initialize the output latch by program as necessary. (4) In halt status The contents of the output latch are output. Because the contents of the output latch are retained, the output data is not affected in the halt status.
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15.6 General-Purpose Output Ports (P0E, P0F, P0X, and P0Y)
15.6.1 Configuration of output ports (P0E, P0F, P0X, and P0Y) (1) through (3) show the configuration of the output ports (P0E, P0F, P0X, and P0Y). (1) P0E (P0E3, P0E2, P0E1, and P0E0 pins) P0F (P0F3, P0F2, P0F1, and P0F0 pins)
LCD/port select flag
VDD
1 0
Output latch Segment signal timing control
Write instruction
Port register (1 bit) Shared by LCD segment register
Read instruction
(2) P0X (P0X5 through P0X0 pins)
LCD/port select flag
VDD
1 0
Output latch Segment signal timing control
Write instruction
Write instruction (PUT)
Port register (1 bit) Shared by LCD segment register
P0X group register (1 bit) Shared by LCD group register
Read instruction Undefined
Read instruction (GET)
(3) P0Y (P0Y15 through P0Y0 pins)
LCD/port select flag
VDD
1 0
Output latch Segment signal key source timing control
Write instruction (PUT)
P0Y group register (1 bit) Shared by key source data register Read instruction (GET) LCD segment register
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15.6.2 Example of using output ports (P0E, P0F, P0X, and P0Y) The pins of P0E, P0F, P0X, and P0Y are set as LCD segment signal output pins on power-ON reset. To use these pins as output port pins, therefore, the port pins to be used must be selected by the P0ESEN, P0FSEN, P0XSEN, or P0YSEN flag of the LCD port select register (LCDPORT: RF address 11H). The port to be used can be selected regardless of P0E, P0F, P0X and P0Y. The pins not set by the LCD port select register as output port pins can be used as LCD segment signal output points. The following 15.6.3 through 15.6.5 describe how to set the output data of P0E, P0F, P0X, and P0Y. 15.6.6 and 15.6.7 describe the configuration and function of the LCD port select register and P0X and P0Y group registers. 15.6.3 Setting data to P0E and P0F To set output data to P0E and P0F, an instruction that writes data to the port register corresponding to the port pin, such as "MOV" instruction, is executed. To output a high level to each pin, "1" is written to the port register. To output a low level, "0" is written to the register. When an instruction that reads the contents of the port register, such as "SKT", is executed, the contents of the output latch are read. Figure 15-3 shows the relation among the P0F port register, LCD segment register, and LCD group register. As shown in this figure, the LCD segment register LCDD14 can be used as a general-purpose data memory when P0F is used. If data is set to the LCD group register LCDR7, the higher 3 bits of P0F are changed. The same applies to P0F. For details, refer to Figure 21-7. Relation among LCD Display Dot, Ports 0E Through 0Y, Key Source Output, and Data Setting Registers in 21. LCD CONTROLLER/DRIVER. Figure 15-3. Relation among P0F Port Register, LCD Segment Register, and LCD Group Register
P0FSEL flag 1 0 1 0 1 0 1 0 Segment signal timing control b1 b0 Segment signal timing control b3 b2 LCDD13 P0F (6DH) x b3 b2 b1 b0 Segment signal timing control b1 b0 Segment signal timing control b3 b2 b7 b6 b5 b4 LCDR7
LCD29/P0F3
LCD28/P0F2
LCDD14 (6EH)
LCD27/P0F1
LCD26/P0F0
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15.6.4 Setting data to P0X To set output data to P0X, the port register or port 0X (P0X) group register may be used. To use the port register, execute an instruction that writes data to the port registers (P0XH and P0XL) corresponding to the port pins, such as "MOV" instruction. To output a high level to each pin, "1" is written to the port register. To output a low level, "0" is written to the register. When an instruction that reads the contents of the port register, such as "SKT", is executed, the contents of the output latch are read. To use the P0X group register, execute the "PUT P0X, DBF" instruction that writes data to the P0X group register (P0X) corresponding to the port pin. When the "GET DBF, P0X" that reads the contents of the P0X group register (P0X) is executed, an "undefined value" is read out. To set data by using the P0X group register, write "1" to output a high level to the port pin, and write "0" to output a low level. Figure 15-4 shows the relation among the P0X port register, P0X group register, LCD segment register, and LCD group register. As shown in this figure, the LCD segment register LCDD10 can be used as a general-purpose data memory when P0X is used. For details, refer to Figure 21-7. Relation among LCD Display Dot, Ports 0E Through 0Y, Key Source Output, and Data Setting Registers in 21. LCD CONTROLLER/DRIVER. Figure 15-4. Relation among P0X Port Register, P0X Group Register, LCD Segment Register, and LCD Group Register
P0XSEL flag 1 0 1 0 1 0 1 0 1 0 1 0 Segment signal timing control b1 b0 Segment signal timing control b3 b2 LCDD8 P0XL (68H) x b3 b2 b1 b0 Segment signal timing control b1 b0 Segment signal timing control b3 b2 LCDD9 P0XH (69H) b7 b6 b5 b4 Segment signal timing control b1 b0 Segment signal timing control b3 b2 x x
b7 b4 b3 b2 b1 b0 LCDR5
LCD21/P0X5
LCD20/P0X4
LCDD10 (6AH) x
LCD19/P0X3
LCD18/P0X2
LCD17/P0X1
LCDR4 P0X
LCD16/P0X0
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15.6.5 Setting data to P0Y To set output data to P0Y, execute the "PUT P0Y, DBF" instruction that writes data to the port 0Y (P0Y) group register corresponding to the port pin. When the "GET DBF, P0Y" instruction that reads the contents of the P0Y group register is executed, the contents of the output latch are read. To output a high level to the port pin, write "1" to the register. To output a low level, write "0". Figure 15-5. Relation among P0Y Port Register, P0Y Group Register, LCD Segment Register, and LCD Group Register
P0YSEL flag LCD15/P0Y15/KS15
1 0
Segment/key source timing control Segment/key source timing control
b7 b3 b2 LCDD7 (67H) b1 b0 b6 LCDR3 b5 b4
b15 b14
LCD14/P0Y14/KS14
1 0
LCD1/P0Y1/KS1
1 0
KSR P0Y
Segment/key source timing control Segment/key source timing control
b3 b3 b2 LCDD0 (60H) b1 b0 x b2 LCDR0 b1 b0 b1 b0
LCD0/P0Y0/KS0
1 0
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15.6.6 Configuration and function of LCD port select register (LCDPORT) The LCD port select register selects whether P0E, P0F, P0X, and P0Y pins are used as LCD segment signal output pins or general-purpose output port pins. The configuration and function of this register are shown below.
Flag Symbol Name b3 P 0 LCD port select register (LCDPORT) Y S E L b2 P 0 X S E L b1 P 0 E S E L b0 P 0 F S E L 11H R/W Address
Read/ Write
Selects LCD segment signal output pins or general-purpose output port pins 0 1 Uses LCD26/P0F0-LCD29/P0F3 pins as LCD segment signal output pins Uses LCD26/P0F0-LCD29/P0F3 pins as general-purpose output port pins
Selects LCD segment signal output pins or general-purpose output port pins 0 1 Uses LCD22/P0E0-LCD25/P0E3 pins as LCD segment signal output pins Uses LCD22/P0E0-LCD25/P0E3 pins as general-purpose output port pins
Selects LCD segment signal output pins or general-purpose output port pins 0 1 Uses LCD16/P0X0-LCD21/P0X5 pins as LCD segment signal output pins Uses LCD16/P0X0-LCD21/P0X5 pins as general-purpose output port pins
Selects LCD segment signal output pins or general-purpose output port pins 0 1 Uses LCD0/P0Y0/KS0-LCD15/P0Y15/KS15 pins as LCD segment signal output port pins Uses LCD0/P0Y0/KS0-LCD15/P0Y15/KS15 pins as general-purpose output port pins
On reset
Power-ON Clock stop CE
0 0
0 0
0 0
0 0
Retained
Ports 0F, 0E, 0X and 0Y can be independently set as general-purpose output ports. The pins not set as general-purpose output port pins can be used as LCD segment signal output pins. The 16 pins LCD0/P0Y0/KS0 through LCD15/P0Y15/KS15 pins multiplex LCD segment signal output and key source signal output. When these pins are set as general-purpose output port pins, the LCD segment signals and key source signals are not output.
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15.6.7 Port 0X (P0X) group register and port 0Y (P0Y) group register (1) and (2) below show the functions of the P0X and P0Y group registers. The P0X and P0Y group registers set the output data of P0X (P0X0 through P0X5 pins) and P0Y (P0Y0 through P0Y15 pins). P0X and P0Y can respectively set 6-bit and 16-bit output data at one time. (1) Function of P0X group register
Name Symbol Address Bit Data DBF3 0CH Data Buffer DBF2 0DH DBF1 0EH DBF0 0FH
b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 Don't care Don't care Transfer data GET sets undefined data PUT can be executed Peripheral Register Name P0X group register b7 b6 b5 b4 b3 b2 b1 b0 Valid data - - Symbol P0X
Peripheral address
8
Peripheral hardware Port 0X
0CH
Don't care
Sets output data of port 0X LCD16/P0X0 pin LCD17/P0X1 pin LCD18/P0X2 pin LCD19/P0X3 pin LCD20/P0X4 pin LCD21/P0X5 pin 0 1 Outputs low level Outputs high level
The output data of port 0X can be set not only by the P0X group register (peripheral address 0CH) but also port registers P0XH and P0XL (69H and 68H of BANK0). If data is set to the P0X group register (peripheral register), the data of the P0XH and P0XL registers (port registers) corresponding to the overlapping bit data are changed to the same value.
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(2) Function of P0Y group register
Name Symbol Address Bit Data DBF3 0CH Data Buffer DBF2 0DH DBF1 0EH DBF0 0FH
b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 Transfer data GET can be executed PUT can be executed Peripheral Register
16
Name P0Y group register
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Valid data
Symbol P0Y
Peripheral address
Peripheral hardware Port 0Y
42H
Sets output data of port 0Y LCD0/P0Y0/KS0 pin LCD1/P0Y1/KS1 pin LCD2/P0Y2/KS2 pin LCD3/P0Y3/KS3 pin LCD4/P0Y4/KS4 pin LCD5/P0Y5/KS5 pin LCD6/P0Y6/KS6 pin LCD7/P0Y7/KS7 pin LCD8/P0Y8/KS8 pin LCD9/P0Y9/KS9 pin LCD10/P0Y10/KS10 pin LCD11/P0Y11/KS11 pin LCD12/P0Y12/KS12 pin LCD13/P0Y13/KS13 pin LCD14/P0Y14/KS14 pin LCD15/P0Y15/KS15 pin 0 1 Outputs low level Outputs high level
Port 0Y is shared with key source signal output pins. Therefore, the P0Y group register (peripheral address 42H) is shared with the key source data register (peripheral address 42H) described later. Therefore, the output data of the port 0Y is set to this register when the LCD0/P0Y0/KS0 through LCD15/P0Y15/KS15 pins are specified as output port pins, and key source signal output data is set to the register when these pins are specified as key source signal output pins.
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15.6.8 Reset status of output ports (P0E, P0F, P0X, and P0Y) (1) On power-ON reset These output port pins are set as LCD segment signal output pins, and output a low level. Because the contents of the output latch are undefined, undefined data is output if these pins are set as output port pins. Initialize the contents of the output latch by program as necessary. (2) On CE reset These pins are set as LCD segment signal output pins, and output a low level. The contents of the output latch are retained. Therefore, previous values can be retained if the pins are set in the output port mode. (3) On execution of clock stop instruction These pins are set as LCD segment signal output pins, and output a low level. The contents of the output latch are retained. Therefore, previous values can be retained if the pins are set in the output port mode. (4) In halt status The contents of the output latch are output. Because the contents of the output latch are retained, the output data is not changed in the halt status.
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16. A/D CONVERTER (ADC)
The A/D converter is used to input an external analog signal as a digital signal.
16.1 Configuration of A/D Converter
Figure 16-1 shows the block diagram of the A/D converter. As shown in this figure, the A/D converter consists of an input select block, a compare voltage generator block, and a compare block. Figure 16-1. Block Diagram of A/D Converter
Control register
Data buffer
P0D3/ADC5 P0D2/ADC4 P0D1/ADC3 P0D0/ADC2 P1D1/ADC1 P1D0/ADC0
6 Input select block Compare block
Compare voltage generator block (R-string D/A converter)
16.2 Functional Outline of A/D Converter
The A/D converter compares the voltage input to the P0D3/ADC5 through P1D0/ADC0 pins with an internal compare voltage, and outputs the result of the comparison as "True (1)" or "False (0)". This comparison result is judged by software. In this way, the A/D converter is used as a successive approximation converter. The following 16.2.1 through 16.2.3 outlines the functions of each block. For details, refer to 16.3 through 16.5. 16.2.1 Input select block This block selects which of the P0D3/ADC5 through P1D0/ADC0 pins is used. The pin to be used is selected by the A/D converter channel select register (ADCCH: RF address 14H). Only one pin can be used at a time. For details, refer to 16.3. 16.2.2 Compare voltage generator block This block generates a compare voltage against which the input voltage is to be compared. The compare voltage is generated by an R-string D/A converter. For details, refer to 16.4.
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16.2.3 Compare block This block compares the input voltage with the internal compare voltage. The result of the comparison is detected by the A/D converter compare judge register (ADCJDG: RF address 06H). For details, refer to 16.5.
16.3 Input Select Block
16.3.1 Configuration of input select block Figure 16-2 shows the configuration of the input select block. Figure 16-2. Configuration of Input Select Block
Control Register 14H Address Bit b3 b2 b1 AAA DDD CCC Flag CCC symbol H H H 321
b0 A D C C H 0
3-6 decoder P0D3/ADC5 P0D2/ADC4 P0D1/ADC3 P0D0/ADC2 0 1 To compare block VADCIN
High ON resistance (for key input) P1D1/ADC1 P1D0/ADC0
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16.3.2 Function of input select block The input select block selects the pin to be used by using the A/D converter channel select register. Only one pin can be used at a time as an A/D converter pin. The pins not used as A/D converter pins can be used as general-purpose input port pins. Although port 0D (P0D3/ADC5 through P0D0/ADC2 pins) are internally connected with a pull-down resistor, the pin selected by the A/D converter channel select register (refer to 16.3.3) is disconnected from the pull-down resistor. The pins not selected remains connected to the pull-down resistor. 16.3.3 Configuration and function of A/D converter channel select register (ADCCH) The A/D converter channel select register selects a pin to be used as the A/D converter pin. The configuration and function of this register are illustrated below.
Flag Symbol Name b3 A D A/D converter channel select register (ADCCH) C C H 3 b2 A D C C H 2 b1 A D C C H 1 b0 A D C C H 0 14H R/W Address
Read/ Write
Selects pin to be used as A/D converter pin 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 P1D0/ADC0 pin P1D1/ADC1 pin P0D0/ADC2 pin P0D1/ADC3 pin P0D2/ADC4 pin P0D3/ADC5 pin A/D converter is not used (general-purpose input port) A/D converter is not used (general-purpose input port)
Fixed to "0"
On reset
Power-ON Clock stop CE
0
1 1
1 1
1 1
Retained
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16.4 Compare Voltage Generator Block
16.4.1 Configuration of compare voltage generator block Figure 16-3 shows the configuration of the compare voltage generator block. Figure 16-3. Configuration of Compare Voltage Generator Block
Data Buffer (DBF) 0CH 0DH 0EH DBF3 DBF2 DBF1 Don't Don't M S care care B 6 A/D converter data register
Address Symbol Data
0FH DBF0 L S B Peripheral address 02H To compare block VREF
Multiplexer 0 1 2 62 63
VDD
1 2R
R
R
3 2R
Reads ADCCMP flag by PEEK
16.4.2 Function of compare voltage generator block The compare voltage generator block switches the multiplexer by using the 6-bit data set to the A/D converter data register (ADCR: peripheral address 02H) and generates a compare voltage. This means that this block is an R-string D/A converter. The compare voltage can be set in 64 steps by the R string (resistance division). The supply voltage of the R-string is the same as the supply voltage VDD of the device. A voltage is supplied to the R-string resistor only when the A/D converter compare judge register described later is detected. The compare voltage is compared with the voltage input to the compare block. The following 16.4.3 describe the configuration and function of the A/D converter data register. Table 16-1 lists the compare voltages.
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16.4.3 Configuration and function of A/D converter data register (ADCR) The A/D converter data register sets the compare voltage of the A/D converter. Because this register is 6 bits long, the lower 6 bits of the data buffer are valid.
Name Symbol Address Bit Data DBF3 0CH Data Buffer DBF2 0DH DBF1 0EH DBF0 0FH
b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 Don't care Don't care Transfer data GET can be executed PUT can be executed Peripheral Register Name A/D converter data register b7 b6 b5 b4 b3 b2 b1 b0 0 0 Valid data Symbol ADCR
Peripheral address
8
Peripheral hardware A/D converter
02H
Sets compare voltage VREF of A/D converter 0 1 VREF = 0 V
x
VREF =
x - 0.5 64
x VDD V
63
Fixed to "0"
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Table 16-1. Set Values of A/D Converter Data Register and Compare Voltages
ADCR Set Data DEC HEX Compare Voltage Logic voltage Unit: x VDD V 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 0 0.5/64 1.5/64 2.5/64 3.5/64 4.5/64 5.5/64 6.5/64 7.5/64 8.5/64 9.5/64 10.5/64 11.5/64 12.5/64 13.5/64 14.5/64 15.5/64 16.5/64 17.5/64 18.5/64 19.5/64 20.5/64 21.5/64 22.5/64 23.5/64 24.5/64 25.5/64 26.5/64 27.5/64 28.5/64 29.5/64 30.5/64 When VDD = 5 V Unit: V 0 0.039 0.117 0.195 0.273 0.352 0.430 0.508 0.586 0.664 0.742 0.820 0.898 0.977 1.055 1.133 1.211 1.289 1.367 1.445 1.523 1.602 1.680 1.758 1.836 1.914 1.992 2.070 2.148 2.227 2.305 2.383 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH ADCR Set Data DEC HEX Compare Voltage Logic voltage Unit: x VDD V 31.5/64 32.5/64 33.5/64 34.5/64 35.5/64 36.5/64 37.5/64 38.5/64 39.5/64 40.5/64 41.5/64 42.5/64 43.5/64 44.5/64 45.5/64 46.5/64 47.5/64 48.5/64 49.5/64 50.5/64 51.5/64 52.5/64 53.5/64 54.5/64 55.5/64 56.5/64 57.5/64 58.5/64 59.5/64 60.5/64 61.5/64 62.5/64 When VDD = 5 V Unit: V 2.461 2.539 2.617 2.695 2.773 2.852 2.930 3.008 3.086 3.164 3.242 3.320 3.398 3.477 3.555 3.633 3.711 3.789 3.867 3.945 4.023 4.102 4.180 4.258 4.336 4.414 4.492 4.570 4.648 4.727 4.805 4.883
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16.5 Compare Block
16.5.1 Configuration of compare block Figure 16-4 shows the configuration of the compare block. Figure 16-4. Configuration of Compare Block
Control Register Address 06H b3 b2 b1 Bit
b0 A D C C M P
Flag symbol
0
0
0
1 2 VDD
Switch 2 Switch 1 VADCIN 2 pF VREF + - Comparator Compare judge FF
16.5.2 Function of compare block The compare block compares voltage VADCIN input from a pin with internal compare voltage VREF by using a comparator and outputs the result to the compare judge FF. The compare judge FF can be detected by reading the ADCCMP flag of the A/D converter compare judge register. The ADCCMP flag is set when VADCIN > VREF, and is reset when VADCIN < VREF. The comparator compares the voltage when the ADCCMP flag is read. In other words, when the ADCCMP flag is read by executing the "PEEK" instruction, switches 1 and 2 are operated to make the comparison. Therefore, the time the A/D converter takes to make comparison once is equivalent to one instruction execution time (4.44 s). The following 16.5.3 describes the configuration and function of the A/D converter compare judge register.
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16.5.3 Configuration and function of A/D converter compare judge register (ADCJDG) The A/D converter compare judge register compares the input voltage VADCIN and compare voltage VREF of the A/D converter. The configuration and function of this register are illustrated below.
Flag Symbol Name b3 b2 b1 b0 A D A/D converter compare judge register (ADCJDG) 0 0 0 C C M P 06H R Address Read/ Write
Detects comparison result of A/D converter 0 1 VADCIN < VREF VADCIN > VREF
Fixed to "0"
On reset
Power-ON Clock stop CE
0
0
0
Undefined Retained Retained
16.6 Performance of A/D Converter
The performance of the A/D converter is as follows: Parameter Resolution Input voltage range Quantized error Performance 1LSB 0 - VDD 62.5 64 Error of offset, gain, non-linearity Note Including quantized error 3 2 LSBNote 1 2 Over range x VDD LSB
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16.7 Using A/D Converter
16.7.1 Comparing one compare voltage Here is a program example: Example To compare the input voltage VADCIN of the ADC0 pin with compare voltage VREF (31.5/64 VDD) and branch to AAA if VADCIN > VREF and branch to BBB if VADCIN < VREF INIT: ADCR7 ADCR6 ADCR5 ADCR4 ADCR3 ADCR2 ADCR1 ADCR0 CLR3 START: INITFLG INITFLG PUT SKT1 BR BR NOT ADCR3, NOT ADCR7, ADCR, DBF ADCCMP AAA BBB NOT ADCR2, NOT ADCR6, NOT ADCR1, ADCR5, NOT ADCR0 NOT ACCR4 FLG FLG FLG FLG FLG FLG FLG FLG 0.0EH.3 0.0EH.2 0.0EH.1 0.0EH.0 0.0FH.3 0.0FH.2 0.0FH.1 0.0FH.0 ; Dummy ; Dummy ; Defines each bit of data buffer as data setting flag of ADCR
ADCCH2, ADCCH1, ADCCH0 ; Sets P1D0/ADC0 pin as A/D converter pin
; Sets compare voltage VREF to 31.5/64 VDD ; Detects ADCCMP flag ; Branches to AAA if ADCCMP flag is False (0) ; Branches to BBB if ADCCMP flag is True (1)
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16.7.2 Successive approximation by binary search The A/D converter can compare only one compare voltage at a time. To convert an input analog voltage into a digital signal, therefore, successive approximation must be executed by program. If the processing time of the successive approximation program differs depending on the input voltage, it is not desirable in some cases because of the relation with the other programs. In these cases, executing binary search as described in (1) through (3) below is convenient. (1) Concept of binary search The concept of binary search is described below. First, the compare voltage is set to 1/2 VDD, and a voltage of 1/4 VDD is added if the result of the comparison is True (if a high level is input) and a voltage of 1/4 VDD is subtracted if the result is False (if a low level is input). In the same way, comparison is sequentially performed by changing the voltage to be added or subtracted to 1/8 VDD and then to 1/16 VDD to 1/64 VDD. If the result of the sixth comparison is False, 1/64 VDD is subtracted and the operation is completed.
1 H H H 3/4 H L Compare voltage (x VDD) 1/2 H H L 1/4 H L 0 1/8 L 1/16 3/16 L 25/32 L 49/64 L 3/8 L 5/16 13/16 H 51/64 L 7/16 H 27/32 L 53/64 L H 55/64 L 5/8 L 9/16 11/16 L 29/32 L 57/64 L 7/8 L 13/16 15/16 H 59/64 L 15/16 H 31/32 L 61/64 L H 63/64 L 1 63/64 62/64 61/64 60/64 59/64 58/64 57/64 56/64 55/64 54/64 53/64 52/64 51/64 50/64 49/64 48/64
First time
Second time
Third time Fourth time
Fifth time
Sixth time
1/64 is subtracted if result is False
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(2) Flowchart of binary search
START Initial setting ADCR 100000B ADCCMP = 1? N Resets b5 of ADCR Sets b4 of ADCR ADCCMP = 1? N Resets b4 of ADCR Sets b3 of ADCR ADCCMP = 1? N Resets b3 of ADCR Sets b2 of ADCR ADCCMP = 1? N Resets b2 of ADCR Sets b1 of ADCR ADCCMP = 1? N Resets b1 of ADCR Sets b0 of ADCR ADCCMP = 1? N Resets b0 of ADCR Detects contents of ADCR : Subtracts 1/64 VDD if result is "0" : Completes conversion if result is "1" Y : Subtracts 1/32 VDD if result is "0" : Adds 1/64 VDD to compare voltage regardless of whether result is "0" or "1" : Detects comparison result Y : Subtracts 1/16 VDD if result is "0" : Adds 1/32 VDD to compare voltage regardless of whether result is "0" or "1" : Detects comparison result Y : Subtracts 1/8 VDD if result is "0" : Adds 1/16 VDD to compare voltage regardless of whether result is "0" or "1" : Detects comparison result Y : Subtracts 1/4 VDD if result is "0" : Adds 1/8 VDD to compare voltage regardless of whether result is "0" or "1" : Detects comparison result Y : Subtracts 1/2 VDD if result is "0" : Adds 1/4 VDD to compare voltage regardless of whether result is "0" or "1" : Detects comparison result Y : Selects pin to be used : Sets compare voltage to 1/2 VDD : Detects comparison result
END
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(3) Program example of binary search (a) Where conversion time is short INIT: ADCR7 ADCR6 ADCR5 ADCR4 ADCR3 ADCR2 ADCR1 ADCR0 CLR3 START: INITFLG INITFLG PUT SKT1 CLR1 SET1 PUT SKT1 CLR1 SET1 PUT SKT1 CLR1 SET1 PUT SKT1 CLR1 SET1 PUT SKT1 CLR1 SET1 PUT SKT1 CLR1 END: NOT ADCR3, NOT ADCR2, NOT ADCR1, NOT ADCR0 NOT ADCR7, NOT ADCR6, ; Detects ADCCMP ; Subtracts 32/64 VDD if ADCCMP is "0" and, ; adds 16/64 VDD ; Detects ADCCMP ; Subtracts 16/64 VDD if ADCCMP is "0" and, ; adds 8/64 VDD ; Detects ADCCMP ; Subtracts 8/64 VDD if ADCCMP is "0" and, ; adds 4/64 VDD ; Detects ADCCMP ; Subtracts 4/64 VDD if ADCCMP is "0" and, ; adds 2/64 VDD ; Detects ADCCMP ; Subtracts 2/64 VDD if ADCCMP is "0" and, ; adds 1/64 VDD ; Detects ADCCMP ; Subtracts 1/64 VDD if ADCCMP is "0" A/D conversion ADCR5, NOT ADCR4 FLG FLG FLG FLG FLG FLG FLG FLG 0.0EH.3 0.0EH.2 0.0EH.1 0.0EH.0 0.0FH.3 0.0FH.2 0.0FH.1 0.0FH.0 ; Dummy ; Dummy ; Defines each bit of data buffer as data setting flag of ADCR
ADCCH2, ADCCH1, ADCCH0 ; Sets P1D0/ADC0 pin as A/D converter pin
ADCR, DBF ; Sets compare voltage to 31.5/64 VDD ADCCMP ADCR5 ADCR4 ADCR, DBF ADCCMP ADCR4 ADCR3 ADCR, DBF ADCCMP ADCR3 ADCR ADCR, DBF ADCCMP ADCR2 ADCR1 ADCR, DBF ADCCMP ADCR1 ADCR0 ADCR, DBF ADCCMP ADCR0
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Number of program steps Number of execution steps A/D conversion time : 31 : 31 : 137.8 s
(b) Where number of program steps is small ADWORK1 ADWORK0 MEM MEM 0.00H 0.01H NOT ADCCH2, NOT ADCCH1, NOT ADCCH0 ; Work area for changing compare voltage
INITFLG START: MOV MOV MOV MOV AD_CHECK: PUT SKT1 BR ADD ADDC BR ADIN_L SUB SUBC ; NEXT_AD: NOP
; Set P1D0/ADC0 pin as A/D converter pin DBF1, #0010B DBF0, #0000B ADWORK1, #0001B ADWORK0, #0000B ADCR, DBF ADCCMP ADIN_L DBF0, ADWORK0 DBF1, ADWORK1 NEXT_AD A/D conversion DBF0, ADWORK0 DBF1, ADWORK1 ; Described to keep A/D ; conversion time constant RORC ADWORK1 RORC ADWORK0 SKT1 BR PUT SKT1 AND : Number of program steps Number of execution steps A/D conversion time : 22 : 58 to 63 : 257.8 to 280 s CY AD_CHECK ADCR, DBF ADCCMP DBF0, #1110B ; 6 bits have been compared? ; Decreases compare voltage ; if ADCCMP flag is "0" ; Increases compare voltage ; if ADCCMP flag is "1" ; Sets compare voltage VREF ; Detects ADCCMP flag ; Sets initial value of compare ; voltage 31.5/64 VDD
After keeping A/D conversion time constant, Number of program steps Number of execution steps A/D conversion time : 23 : 63 : 280 s
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16.8 Notes on Using A/D Converter
When the P0D3/ADC5 to P0D0/ADC2 pin is used as the A/D converter pin and when it is specified that the halt status be released by key input, the halt status may not be set. This is because the pin set as the A/D converter pin is disconnected from the latch of the input port as described in 12.4 Halt Function. Figure 16-5 below shows the relation between the P0D3/ADC5 through P0D0/ADC2 pins and the input latch. As shown in this figure, if a high level happens to be input to an A/D converter pin set by the A/D converter select signal, the input latch retains "1". Therefore, even if it is specified that the halt status be released by key input, it is judged that a high level is input to this pin, and the halt status is released as soon as it has been set. Figure 16-5. Relation between P0D3/ADC5 through P0D0/ADC2 Pins and Input Latch
P0Dn/ADCm VDD
To A/D converter
Input latch
To port register
A/D converter select signal
16.9 Reset Status
16.9.1 On power-ON reset All the P0D3/ADC5 through P0D0/ADC2 pins and P1D1/ADC1 and P1D0/ADC0 pins are set in the general-purpose input port mode. 16.9.2 On execution of clock stop instruction All the P0D3/ADC5 through P0D0/ADC2 pins and P1D1/ADC1 and P1D0/ADC0 pins are set in the general-purpose input port mode. 16.9.3 On CE reset The pin selected as the A/D converter pin is retained as is.
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17. D/A CONVERTER (DAC)
The D/A converter (DAC) outputs signals by means of variable-duty PWM (Pulse Width Modulation). By connecting an external lowpass filter to the D/A converter, digital signals can be converted into analog signals.
17.1 Configuration of D/A Converter
Figure 17-1 shows the block diagram of the D/A converter. As shown in this figure, the D/A converter consists of an output select block and a duty setting block for each pin, and a clock generation block. Figure 17-1. Block Diagram of D/A Converter
Control register
Data buffer
P1B3/PWM2
Output select block
Duty setting block
fPWM2 Clock generation block
P1B2/PWM1
Output select block
Duty setting block
fPWM1
P1B1/PWM0
Output select block
Duty setting block
fPWM0
17.2 Functional Outline of D/A Converter
Each pin of the D/A converter outputs a variable-duty signal independently of the other pins. The output frequency is 4394.5 Hz, and the duty factor can be changed in 256 steps. The following 17.2.1 through 17.2.3 outline the functions of the respective blocks. 17.2.1 Output select block An output select block specifies whether each pin is used as a general-purpose output port pin or D/A converter pin. This selection is made by using the PWM mode select register (PWMMODE: RF address 13H) (refer to 17.3). 17.2.2 Duty setting block A duty setting block outputs a variable-duty signal whose duty factor can be changed in 256 steps. The duty factor of each pin is independently set by the PWM data register (PWMR0, PWMR1, or PWMR2: peripheral address 05H, 06H, or 07H) via data buffer (refer to 17.4).
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17.2.3 Clock generation block The clock generation block generates the basic clock that is used to set a duty factor (refer to 17.4). The frequency fPWM of the generated clock is 1125 kHz.
17.3 Output Select Block
17.3.1 Configuration of output select block Figure 17-2 shows the configuration of the output select block. Figure 17-2. Configuration of Output Select Block
Control Register Address Bit b3 P W M Flag symbol 2 S E L 13H b2 P W M 1 S E L b1 P W M 0 S E L b0 C G P S E L
P1B3/PWM2 1 0 Duty setting block Output latch
P1B2/PWM1 1 0 Duty setting block Output latch
P1B1/PWM0 1 0 Duty setting block Output latch
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17.3.2 Function of output select block The output select block selects whether the P1B3/PWM2 through P1B1/PWM0 pins are used as general-purpose output port pins or D/A converter pins. This selection is made by the PWM2SEL, PWM1SEL, and PWM0SEL flags of the PWM mode select register. Each pin is selected independently of the others. The P1B3/PWM2 through P1B1/PWM0 pins are N-ch open-drain output pins and therefore, must be connected with external pull-up resistors. The following 17.3.3 describe the configuration and function of the PWM mode select register. 17.3.3 Configuration and function of PWM mode select register (PWMMODE) The PWM mode select register selects a pin that is used for the D/A converter (PWM output) or clock generator port (CGP). The configuration and function of this register are illustrated below. For the details of the CGP, refer to 18. CLOCK GENERATOR PORT (CGP).
Flag Symbol Name b3 P W PWM mode select register (PWMMODE) M 2 S E L b2 P W M 1 S E L b1 P W M 0 S E L b0 C G P S E L 13H R/W Address Read/ Write
Selects general-purpose output port or clock generator port 0 1 P1B0/CGP pin is used as general-purpose output port P1B0/CGP pin is used as clock generator port
Selects general-purpose output port or D/A converter (PWM output) 0 1 P1B1/PWM0 pin is used as general-purpose output port P1B1/PWM0 pin is used as D/A converter
Selects general-purpose output port or D/A converter (PWM output) 0 1 P1B2/PWM1 pin is used as general-purpose output port P1B2/PWM1 pin is used as D/A converter
Selects general-purpose output port or D/A converter (PWM output) 0 1 P1B3/PWM2 pin is used as general-purpose output port P1B3/PWM2 pin is used as D/A converter
On reset
Power-ON Clock stop CE
0 0
0 0
0 0
0 0
Retained
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17.4 Duty Setting Block and Clock Generation Block
17.4.1 Configuration of duty setting block and clock generation block Figure 17-3 shows the configuration of the duty setting block and clock generation block. Figure 17-3. Configuration of Duty Setting Block and Clock Generation Block
Data Buffer (DBF) Address Symbol Data 0CH DBF3 Don't care 0DH DBF2 Don't care 0EH DBF1 M S B 0FH DBF0 L S B
Peripheral address 07H 8 PWM2 data register (PWMR2)
To output block
Comparator Counter (8 bits) fPWM2 1125 kHz
Peripheral address 06H 8 PWM1 data register (PWMR1) Clock generation block
To output block
Comparator Counter (8 bits) fPWM1 1125 kHz
Peripheral address 05H 8 PWM0 data register (PWMR0)
To output block
Comparator Counter (8 bits) fPWM0 1125 kHz
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17.4.2 Function and operation of clock generation block The clock generation block outputs the basic clocks (fPWM2, fPWM1, and fPWM0) to set the duty factors of the output signals (PWM2, PWM1, and PWM0 pins). The output frequencies of all fPWM2, fPWM1, and fPWM0 are 1125 kHz (0.89 s). However, there are the following phase differences among fPWM2, fPWM1, and fPWM0.
fPWM2 fPWM1 fPWM0 0.22 s 0.22 s 0.89 s
17.4.3 Function and operation of duty setting block The duty setting block compares the values set to the respective PWM data registers (PWM2, PWM1, and PWM0) with the values of the basic clocks (fPWM2, fPWM1, and fPWM0) counted by the respective 8-bit counters, and outputs a high level if the value of the PWM register is greater or a low level if the value of the PWM register is smaller. Where the value set to the PWM register is "x", therefore, the duty factor is as follows: x + 0.25 256 0.25 is an offset, and a high level is output even when x = 0. Because the frequency of the basic clock is 1125 kHz, the frequency and cycle of the output signal are as follows: 1125 kHz 256 256 1125 kHz Data is set to each PWM data register independently via data buffer. Therefore, a signal with a different duty factor can be output by each pin. The following 17.4.4 and 17.4.5 describe the configuration and function of the PWM data register, and relation between the output waveform and duty factor of each pin.
Duty: D =
x 100%
Frequency:
f=
= 4394.5 Hz
Cycle:
t=
= 227.6 s
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17.4.4 Configuration and function of each PWM data register The function of each PWM data register is illustrated below. The PWM data register sets the duty factor of the output signal (PWM output) of the D/A converter.
Name Symbol Address Bit Data DBF3 0CH Data Buffer DBF2 0DH DBF1 0EH DBF0 0FH
b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 Don't care Don't care Transfer data GET can be executed PUT can be executed Peripheral Register Name PWM0 data register b7 b6 b5 b4 b3 b2 b1 b0 Valid data Symbol PWMR0
Peripheral address
8
Peripheral hardware PWM0 pin
05H
PWM1 data register
PWMR1
06H
PWM1 pin
PWM2 data register
PWMR2
07H
PWM2 pin
Sets PWM output duty of each pin 0 Duty: D = x + 0.25 256 x 100%
x
Frequency: f =
1125 256
kHz
= 4394.5 Hz 255
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17.4.5 Relation between output waveform of D/A converter and each pin (1) shows the relation between the duty factor and output waveform. (2) shows the relation of the output waveform of each pin. (1) Duty and output waveform
x=0 x=1 x=2 0.89 s 0.22 s 0.89 s
x = 255 0.67 s 227.6 s
(2) Output waveform of each pin
PWM2 (x = 0) PWM1 (x = 0) PWM0 (x = 0) 0.22 s 227.6 s
17.5 Reset Status
17.5.1 On power-ON reset The P1B3/PWM2 through P1B1/PWM0 pins are specified as the general-purpose output port pins. The output value is "undefined". The value of each PWM data register is "undefined". 17.5.2 On execution of clock stop instruction The P1B3/PWM2 through P1B1/PWM0 pins are specified as the general-purpose output port pins. The output value is the "previous contents of the output latch". Each PWM data register retains the previous value. 17.5.3 On CE reset The P1B3/PWM2 through P1B1/PWM0 pins retain the previous output status. Therefore, the pin used as a D/A converter pin retains the PWM output. 17.5.4 In halt status The P1B3/PWM2 through P1B1/PWM0 pins retain the previous output status. Therefore, the pin used as a D/A converter pin retains the PWM output.
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18. CLOCK GENERATOR PORT (CGP)
The clock generator port outputs signals in two modes: VDP (Variable Duty Pulse) mode in which the duty factor is changed, and SG (Signal Generator) mode in which the frequency is changed.
18.1 Configuration of Clock Generator Port
Figure 18-1 shows the block diagram of the clock generator port. As shown in this figure, the clock generator port consists of an output select block, a VDP/SG setting block, and a clock generation block. Figure 18-1. Block Diagram of Clock Generator Port
Control register
Data buffer
P1B0/CGP
Output select block
VDP/SG setting block
fCGP
Clock generation block
18.2 Functional Outline of Clock Generator Port
The clock generator port outputs a variable-duty signal (VDP function) or variable-frequency signal (SG function) from the P1B0/CGP pin. The VDP function can changes the duty factor in 64 steps. The SG function can changes the frequency in 64 steps. The following 18.2.1 through 18.2.3 outline the functions of the respective blocks. Because the clock generator port is shares the hardware with the frequency counter that is described later, the clock generator and frequency counter cannot be used at the same time. For details, refer to 18.7. 18.2.1 Output select block The output select block selects whether the P1B0/CGP pin is used as a general-purpose output port pin or the clock generator port. This selection is made by the PWM mode select register (PWMMODE: RF address 13H). For details, refer to 18.3. 18.2.2 VDP/SG setting block The VDP/SG setting block selects the VDP or SG function, and outputs a variable-duty signal when the VDP function is selected and a variable-frequency signal when the SG function is selected. The duty factor when the VDP function is selected and the frequency when the SG function is selected is selected by the CGP data register (CGPR: peripheral address 20H) via data buffer. For details, refer to 18.4.
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18.2.3 Clock generation block The clock generation block generates a basic clock that is used to set a duty factor for the VDP function or a frequency for the SG function. The frequency fCGP of the generated clock is 18 kHz. For details, refer to 18.4.
18.3 Output Select Block
18.3.1 Configuration of output select block Figure 18-2 shows the configuration of the output select block. Figure 18-2. Configuration of Output Select Block
Control Register Address Bit b3 P W M Flag symbol 2 S E L 13H b2 P W M 1 S E L VDD 1 0 Output latch VDP/SG setting block b1 P W M 0 S E L b0 C G P S E L
P1B0/CGP
18.3.2 Function of output select block The output select block selects whether the P1B0/CGP pin is used as a general-purpose output port pin or the clock generator port. This selection is made by the CGPSEL flag of the PWM mode select register. The following 18.3.3 describes the configuration and function of the PWM mode select register.
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18.3.3 Configuration and function of PWM mode select register (PWMMODE) The PWM mode select register selects pins that are used as a D/A converter pins and clock generator port. The configuration and function of this register are shown below. For the details of the D/A converter, refer to 17. D/A CONVERTER (DAC).
Flag Symbol Name b3 P W PWM mode select register (PWMMODE) M 2 S E L b2 P W M 1 S E L b1 P W M 0 S E L b0 C G P S E L 13H R/W Address Read/ Write
Selects general-purpose output port or clock generator port 0 1 P1B0/CGP pin is used as general-purpose output port P1B0/CGP pin is used as clock generator port
Selects general-purpose output port or D/A converter (PWM output) 0 1 P1B1/PWM0 pin is used as general-purpose output port P1B1/PWM0 pin is used as D/A converter
Selects general-purpose output port or D/A converter (PWM output) 0 1 P1B2/PWM1 pin is used as general-purpose output port P1B2/PWM1 pin is used as D/A converter
Selects general-purpose output port or D/A converter (PWM output) 0 1 P1B3/PWM2 pin is used as general-purpose output port P1B3/PWM2 pin is used as D/A converter
On reset
Power-ON Clock stop CE
0 0
0 0
0 0
0 0
Retained
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18.4 VDP/SG Setting Block and Clock Generation Block
18.4.1 Configuration of VDP/SG setting block and clock generation block Figure 18-3 shows the configuration of the VDP/SG setting block and clock generation block. Figure 18-3. Configuration of VDP/SG Setting Block and Clock Generation Block
Data Buffer (DBF) 0CH 0DH 0EH DBF3 DBF2 DBF1 Don't Don't M S care care B Control Register 12H Address
Address Symbol Data
0FH DBF0 L S B
Bit Flag symbol
7 Peripheral address 20H 6 CGP data register (CGPR) 1
b3 I F C M D 1
b2 I F C M D 0
b1 I F C C K 1
b0 I F C C K 0
2-4 decoder Frequency counter C G P
VDP/SG select VDP 0 1 VDP SG 1/2 6-bit CGP counter (multiplexed with IF counter) IFC SG
Output block
Comparator
Clock generation block (18 kHz) fCGP
CGP
18.4.2 Function and operation of clock generation block The clock generation block outputs a basic clock (fCGP) that is used to set a duty factor for the VDP function and a frequency for the SG function. The output frequency is 18 kHz.
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18.4.3 Function and operation of VDP/SG setting block The VDP/SG setting block selects the VDP or SG function, and sets a duty factor for the VDP function or a frequency for the SG function. The 6-bit counter (CGP counter) of the VDP/SG setting block is multiplexed with an IF counter that is described later, either the CGP function or frequency counter can be selected by the IF counter mode select register (IFCMODE: RF address 12H). (Refer to 18.4.4) (1) and (2) below describe the operations of the VDP function and SG function. Data is set to the CGP data register (refer to 18.4.5) via data buffer. The following 18.4.6 shows the output waveforms of the VDP and SG functions. 18.4.7 lists the set values of the CGP data register, duty factors of the VDP function, and frequencies of the SG function. (1) VDP function When the VDP function is selected, the value set to the higher 6 bits of the CGP data register is compared with the value of the basic clock (fCGP) counted by the CGP counter. If the value of the CGP data register is greater, a high level is output; if the value of the CGP data register is smaller, a low level is output. Where the value "x" set to the CGP register is "x", the duty factor DVDP is as follows: x+2 67 "2" is an offset and a pulse is output even when x = 0. Because the frequency of the basic clock is 18 kHz, the frequency fVDP and cycle tVDP of the output signal are as follows: 18 kHz 67 Cycle: tVDP = 67 18 kHz (2) SG function The SG function compares the value set to the higher 6 bits of the CGP data register with the basic clock (fCGP) counted by the CGP counter, and outputs a signal when the clock counts reaches "0". Where the value set to the CGP register is "x", the output frequency fSG is as follows: 18 2(x + 2) "2" is an offset and a pulse is output even when x = 0. The duty factor DSG is 50% as follows because a 1/2 divider is used: Duty: DSG = 50% = 3722.2 s
Duty:
DVDP =
x 100%
Frequency:
fVDP =
= 268.7 Hz
Frequency:
fSG =
kHz
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18.4.4 Configuration and function of IF counter mode select register (IFCMODE) The IF counter mode select register sets the functions of the frequency counter (IF counter and external gate counter) and clock generator port. The configuration and function of this register are illustrated below.
Flag Symbol Name b3 I F IF counter mode select register (IFCMODE) C M D 1 b2 I F C M D 0 b1 I F C C K 1 b0 I F C C K 0 12H R/W Address Read/ Write
Sets gate time of IF counter and reference frequency of external gate counter Gate time of IF counter 0 0 1 1 0 1 0 1 1 ms 4 ms 8 ms Open
Reference frequency of external gate counter
1 kHz 100 kHz 900 kHz 0 kHz
Selects functions of IF counter, external gate counter (FCG), and clock generator port (CGP) 0 0 1 1 0 1 0 1 Clock generator port (CGP) IF counter (FMIFC) IF counter (AMIFC) External gate counter (FCG)
On reset
Power-ON Clock stop CE
0 0
0 0
0 0
0 0
Retained
The frequency counter and clock generator port cannot be used at the same time. To use the clock generator port, reset the IFCMD1 and IFCMD0 flags to "0". After resetting these flags to "0", the CGPSEL flag of the output select block must be set to "1".
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18.4.5 Configuration and function of CGP data register The configuration and function of the CGP data register are illustrated below. The CGP data register selects the VDP or SG function, and sets a duty factor for the VDP function and a frequency for the SG function.
Name Symbol Address Bit Data DBF3 0CH Data Buffer DBF2 0DH DBF1 0EH DBF0 0FH
b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 Don't care Don't care Transfer data GET can be executed PUT can be executed Peripheral Register Name CGP data register b7 b6 b5 b4 b3 b2 b1 b0 Valid data 0 Symbol CGPR
Peripheral address
8
Peripheral hardware Clock generator port (CGP)
20H
Fixed to "0"
Selects SG or VDP function 0 1 VDP function SG function
Sets duty factor for VDP function and frequency for SG function 0 VDP function Duty: D = x x+2 x 100% 67 Frequency: f = 269 Hz
SG function Frequency: f = 18 kHz 2(x + 2)
63
Duty: D = 50%
The CGP counter is multiplexed with the higher 6 bits of the IF counter that is described in 20. FREQUENCY COUNTER (FC). Therefore, the frequency counter and clock generator port cannot be used at the same time. For details, refer to 18.7.
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18.4.6 Output waveforms of VDP and SG functions (1) shows the relation between the duty factor and output waveform of the VDP function. (2) shows the output waveform of the SG function. (1) Duty factor and output waveform of VDP function
x=0 x=1 x=2 111.1 s 55.6 s 55.6 s
x = 63 111.1 s 3722.2 s
(2) Output waveform of SG function
(x + 2)/18 ms 2 (x + 2)/18 ms
(x + 2)/18 ms
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18.4.7 List of set values of CGP data register (CGPR) and duty factors of VDP and frequencies of SG
CGPR Set Data (higher 6 bits) DEC 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 HEX 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH Duty Factor of VDP Function Frequency of SG Function CGPR Set Data (higher 6 bits) Duty Factor of VDP Function Frequency of SG Function
HEX 00H 04H 08H 0CH 10H 14H 18H 1CH 20H 24H 28H 2CH 30H 34H 38H 3CH 40H 44H 48H 4CH 50H 54H 58H 5CH 60H 64H 68H 6CH 70H 74H 78H 7CH 2/67 3/67 4/67 5/67 6/67 7/67 8/67 9/67 10/67 11/67 12/67 13/67 14/67 15/67 16/67 17/67 18/67 19/67 20/67 21/67 22/67 23/67 24/67 25/67 26/67 27/67 28/67 29/67 30/67 31/67 32/67 33/67
HEX 02H 06H 0AH 0EH 12H 16H 1AH 1EH 22H 26H 2AH 2EH 32H 36H 3AH 3EH 42H 46H 4AH 4EH 52H 56H 5AH 5EH 62H 66H 6AH 6EH 72H 76H 7AH 7EH
(Hz) 4500.000 3000.000 2250.000 1800.000 1500.000 1285.714 1125.000 1000.000 900.000 818.182 750.000 692.308 642.857 600.000 562.500 529.412 500.000 473.684 450.000 428.571 409.091 391.304 375.000 360.000 346.154 333.333 321.429 310.345 300.000 290.323 281.250 272.727
DEC 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
HEX 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH
HEX 80H 84H 88H 8CH 90H 94H 98H 9CH A0H A4H A8H ACH B0H B4H B8H BCH C0H C4H C8H CCH D0H D4H D8H DCH E0H E4H E8H ECH F0H F4H F8H FCH 34/67 35/67 36/67 37/67 38/67 39/67 40/67 41/67 42/67 43/67 44/67 45/67 46/67 47/67 48/67 49/67 50/67 51/67 52/67 53/67 54/67 55/67 56/67 57/67 58/67 59/67 60/67 61/67 62/67 63/67 64/67 65/67
HEX 82H 86H 8AH 8EH 92H 96H 9AH 9EH A2H A6H AAH AEH B2H B6H BAH BEH C2H C6H CAH CEH D2H D6H DAH DEH E2H E6H EAH EEH F2H F6H FAH FEH
(Hz) 264.706 257.143 250.000 243.243 236.842 230.769 225.000 219.512 214.286 209.302 204.545 200.000 195.652 191.489 187.500 183.673 180.000 176.471 173.077 169.811 166.667 163.636 160.714 157.895 155.172 152.542 150.000 147.541 145.161 142.857 140.625 138.462
CGPR 1 CGPR 0 CGPR - - VDP/SG setting bit 0 0
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18.5 Using Clock Generator
The following 18.5.1 and 18.5.2 describe how to use the VDP and SG functions. 18.5.1 VDP function An program example of using the VDP function is shown below. As shown in this example, execute the "SET1 CGPSEL" instruction that sets the P1B0/CGP pin as the CGP output pin after setting data to the CGP data register. This is because if the contents of the CGP data register happens to be undefined (especially, at power-ON reset) when the "SET1 CGPSEL" instruction has been executed, an undefined signal is output. Example To output a signal with a duty factor of 10/67 VDPDUTY CLR2 MOV MOV PUT SET1 DAT 20H IFCMD1, IFCMD0 ; Defines VDP function and data with duty factor = 10/67 ; Sets 6-bit counter as CGP
DBF1, #VDPDUTY SHR 4 AND 0FH DBF0, #VDPDUTY AND 0FH CGPR, DBF CGPSEL ; Sets VDP function and duty to CGP data register ; Sets P1B0/CGP pin as CGP output pin ; Execute this instruction after setting data to CGP data register.
18.5.2 SG function A program example of using the SG function is shown below. When using the SG function, execute the "SET1 CGPSEL" instruction that sets the P1B0/CGP as the CGP output pin after setting data to the CGP data register, in the same manner as in the example in 18.5.1. This is because if the contents of the CGP data register happens to be undefined (especially, at power-ON reset) when the "SET1 CGPSEL" instruction has been executed, an undefined signal is output. Example To output a signal with a frequency of 900 Hz SGFRQ CLR2 MOV MOV PUT SET1 DAT 22H IFCMD1, IFCMD0 ; Defines SG function and data with frequency = 900 Hz ; Sets 6-bit counter as CGP
DBF1, #SGFRQ SHR 4 AND 0FH DBF0, #SGFRQ AND 0FH CGPR, DBF CGPSEL ; Sets SG function and frequency to CGP data register ; Sets P1B0/CGP pin as CGP output pin ; Execute this instruction after setting data to CGP data register.
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18.6 Reset Status
18.6.1 On power-ON reset The P1B0/CGP pin is specified as a general-purpose output port pin because the CGPSEL flag is reset. Because the value of the latch of the output port is "undefined", undefined data is output. The value of the CGP data register is "undefined". 18.6.2 On execution of clock stop instruction The P1B0/CGP pin is specified as a general-purpose output port pin because the CGPSEL flag is reset. Because the value of the latch of the output port is the "previous contents of the output latch", the value of the latch is output. The value of the CGP data register retains the previous value. 18.6.3 On CE reset The P1B0/CGP pin retains the previous output status. 18.6.4 In halt status The P1B0/CGP pin retains the previous output status.
18.7 Notes on Using Clock Generator Port
The 6-bit CGP counter that sets the duty factor (for the VDP function) and frequency (for the SG function) of the clock generator port is multiplexed with the IF counter described in 20. FREQUENCY COUNTER (FC). Therefore, the clock generator port and frequency counter cannot be used at the same time. If the data of the IF counter mode select register and IF counter data register (IFC: peripheral address 43H) are manipulated when the clock generator port is used, the operation described in 18.7.1 is performed. If the data of the IF counter mode select register and CGP data register are manipulated when the frequency counter is used, the operation described in 18.7.2 is performed. 18.7.1 When clock generator port is used (1) If IFCMD1 and IFCMD0 flags of IF counter mode select register are manipulated If a value other than "0" is written to the IFCMD1 and IFCMD0 flags, the P1B0/CGP pin retains the current output level when the data has been set, and stops the CGP operation. If the flags are reset to "0", the CGP operation is started. (2) If IF counter data register is manipulated The CGP operation is not affected even if the IF counter data register is read (by the GET instruction) or written (by the PUT instruction). When the register is read, an "undefined" value is read. Nothing is changed even if the register is written. However, because the IF counter data register is a read-only peripheral register, do not write anything to this register.
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18.7.2 When frequency counter is used (1) If IFCMD1 and IFCMD0 flags of IF counter mode select register are manipulated If "0" is written to the IFCMD1 and IFCMD0 flags, the P1B0/CGP pin performs the operation specified by the CGP data register at that time when the data has been set. To perform the CGP operation, however, the CGPSEL flag of the PWM mode select register must also be set. If the IFCMD1 and IFCMD0 flags are set to the previous value, the frequency counter continues operation, but the count value is not accurate. In other words, frequency counting is not performed while the CGP operation is selected. (2) When CGP data register is manipulated The frequency counter is not affected even if it is read (by the GET instruction) or written (by the PUT instruction). When the counter is read, the value set when the CGP function was previously used ("undefined value" if the CGP function was not used) is read. When it is written, the contents of bits 3 through 1 of DBF1 and DBF0 are written to the CGP data register.
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19. SERIAL INTERFACE
The serial interface is used to transfer serial data in 8-bit units with an external device.
19.1 Configuration of Serial Interface
Figure 19-1 shows the block diagram of the serial interface. As shown in this figure, the serial interface consists of two channels: serial interface 0 (SIO0) and serial interface 1 (SIO1). Serial interfaces 0 and 1 respectively consist of an I/O control circuit, a presettable shift register, a clock control block, a clock generation block, and an interrupt block. Figure 19-1. Block Diagram of Serial Interface
Control register
Data buffer
Peripheral address 04H
P0A3/SDA P0A2/SCL P0A1/SCK0 P0A0/SO0 P0B3/SI0
I/O control
Presettable shift register 0
Clock control Serial interface 0
Clock generation
Interrupt block
Peripheral address 03H
I/O control
P0B2/SCK1 P0B1/SO1 P0B0/SI1
Presettable shift register 1
Clock control Serial interface 1
Clock generation
260
PD17010
19.2 Functional Outline of Serial Interface
Table 19-1 shows the classification and communication mode of the serial interface. As shown in this table, two serial interface channels, 0 (SIO0) and 1 (SIO1), are provided. Serial interfaces 0 and 1 can be used simultaneously. Serial interface 0 can be used in two-line or three-line mode. In the two-line mode, the P0A3/SDA and P0A2/SCL pins are used, and the P0A1/SCK0, P0A0/SO0, and P0B3/SI0 pins are used in the three-line mode. Moreover, the I2C busNote and serial I/O mode can be selected in the two-line mode. Serial interface 1 can be used only in the three-line mode, in which the P0B2/SCK1, P0B1/SO1, and P0B0/SI1 pins are used. The communication mode in this mode is the serial I/O mode. Serial interface 0 is controlled by the following control registers: * Serial I/O0 mode select register * Serial I/O0 wait control register * Serial I/O0 wait status judge register * Serial I/O0 status judge register * Serial I/O0 interrupt mode register * Serial I/O0 clock select register registers. Serial out data is set to and serial in data is read from serial interfaces 0 and 1 by the presettable shift registers 0 (SIO0SFR: peripheral address 04H) and 1 (SIO1SFR: peripheral address 03H) via data buffer. The following 19.3 through 19.12 describe serial interface 0. 19.13 through 19.21 describe serial interface 1. Note When using the I2C bus mode (including when it is realized by program without using the peripheral hardware), advise NEC when you place an order for mask. Table 19-1. Classification and Communication Modes of Serial Interface
Serial interface Classification by Hardware Serial interface 0 (SIO0) 3 lines Number of Lines 2 lines I2C bus mode Serial I/O mode Serial I/O mode P0A3/SDA P0A2/SCL P0A1/SCK0 P0A0/SO0 P0B3/SI0 Serial interface 1 (SIO1) 3 lines Serial I/O mode P0B2/SCK1 P0B1/SO1 P0B0/SI1 Communication Mode Pins Used
(SIO0MODE : RF address 08H) (SIO0WT (SIO0STUS (SIO0INT (SIO0CLK : RF address 18H) : RF address 28H) : RF address 38H) : RF address 39H) (SIO0WSTR : RF address 19H)
Serial interface 1 is controlled by the serial I/O1 mode select register (SIO1MODE: RF address 02H) of the control
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19.3 Configuration of Serial Interface 0 (SIO0)
Figure 19-2 shows the block diagram of serial interface 0. As shown in this figure, the shift clock control block of the serial interface 0 consists of a clock I/O pin block, a clock generation block, a wait control block, a clock count block, a start/stop detection block, and an interrupt control block. The serial data control block consists of a serial data I/O pin block, a presettable shift register 0, and an acknowledge block. These blocks are controlled by the flags of control registers. Data is written to or read from the presettable shift register 0 via data buffer. 19.4 outlines the functions of the respective blocks.
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Figure 19-2. Block Diagram of Serial Interface 0
Control Register 19H 18H
S I O 0 0 W S T T SSS BII AOO C00 KNW WR TQ 1 S I O 0 W R Q 0
Address
S I O 0 C H
08H
S B S I O 0 M S
39H
SSSSS IIIII OOOOO 00000 TCCCC XKKKK 3210
28H
SSS IIB OOS 00T SST FF 89 S B B S Y
38H
SSS I II OOO 000 I II MMM DDD 321 S I O 0 I M D 0
Flag symbol Shift clock l/O pin block
0
0
P0A2/ SCL
P0A2/SCL output control
Output latch
WRITE Port register READ
P0ABIO2 flag P0A1/ SCK0
P0A1/SCK0 output control Output latch
Wait signal
START WAIT
SF8 SF7
WRITE Port register READ
Shift clock
CLKOUT Output Clock control
SF8 Wait SF9 control
SF7 SF8 SF9 Clock counter START STOP Start/stop detection
START STOP Interrupt control
P0ABIO1 flag Shift clock input Serial data l/O pin block
P0A3/ SDA
P0A3/SDA output control
Output latch
WRITE Port register READ
P0ABIO3 flag
Data Buffer (DBF)
P0A0/ SO0
P0A0/SO0 output control
Output latch
WRITE Port register READ
Address Signal Data
0CH DBF3
0DH DBF2
0EH DBF1 M S B
0FH DBF0 L S B
Peripheral address 04H P0ABIO0 flag P0B3/ SI0
Output latch WRITE Port register READ
DATAOUT
Presettable shift register 0
CLKIN DATAIN
P0BBIO3 flag
Serial out data Serial in data
Acknowledge control
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19.4 Functional Outline of Serial Interface 0
Serial interface 0 can be used in two modes in terms of the number of pins as shown in Table 19-1: three-line and two-line modes. In the two-line mode, the P0A3/SDA and P0A2/SCL pins are used, and the P0A1/SCK0, P0A0/SO0, and P0B3/SI0 pins are used in the three-line mode. In the two-line mode, two communication modes, I2C bus and serial I/O modes can be selected. Only the serial I/O mode can be used in the three-line mode. In the I2C bus and serial I/O modes, an internal clock (master) or external clock (slave) operation can be selected. Moreover, reception (RX) or transmission (TX) operation can be selected. In the I2C bus mode, serial communication between two or more devices can be executed with two lines. The following 19.4.1 through 19.4.9 outline the functions of the respective blocks shown in Figure 19-2. For the details of the respective blocks, refer to 19.5 through 19.10. 19.4.1 Shift clock I/O pin block This block selects a shift clock I/O pin. The shift clock I/O pin is selected by the serial I/O0 mode register. For details, refer to 19.5. 19.4.2 Serial data I/O pin block This block selects a serial data I/O pin. The serial data I/O pin is selected by the serial I/O0 mode select register. For details, refer to 19.5. 19.4.3 Clock generation block This block selects the clock frequency of the shift clock and controls the shift clock output timing. The clock frequency is selected by the serial I/O0 clock select register. For details, refer to 19.6. 19.4.4 Clock counter This counter counts the rising edges of the clock output by the shift clock output pin and outputs a signal at the seventh clock (SF7 signal), eighth clock (SF8 signal), and ninth clock (SF9 signal). These signals are used to control wait (pause) cycle of serial communication and interrupt. The eighth clock (SF8) and ninth clock (SF9) signals can be detected by the serial I/O0 status judge register. For details, refer to 19.7. 19.4.5 Start/stop detection block This block detects a start and stop conditions in the I2C bus mode. It does not operate in the serial I/O mode. The start and stop conditions can be detected by the SBSTT and SBBSY flags of the serial I/O0 status judge register. For details, refer to 19.7.
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19.4.6 Presettable shift register 0 (SIO0SFR) This shift register sets serial out data and stores serial in data. It performs a shift operation in response to the clock input or output to the shift clock input pin, and inputs or outputs data. The output data is set and the input data is read via data buffer. For details, refer to 19.8. 19.4.7 Wait control block This block controls the wait (pause) and wait release (communication operation) states of serial communication. The wait condition is set by the serial I/O0 wait control register SIO0WRQ1 and SIO0WRQ0 flag, and the wait state is released by the SIO0NWT flag. For details, refer to 19.9. 19.4.8 Acknowledge block This block controls the acknowledge signal when the I2C bus mode is used. It does not operate in the serial I/O mode. The acknowledge signal is set or read by the SBACK flag of the serial I/O0 wait control register. For details, refer to 19.9. 19.4.9 Interrupt control block This block issues an interrupt request signal in response to signals from the clock counter and start/stop detection block. The condition under which the interrupt request is issued is specified by the SIO0IMD3 through SIO0IMD0 flags of the serial I/O0 interrupt mode register. For details, refer to 19.10.
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19.5 Shift Clock and Serial Data I/O Pin Control Block
The shift clock and data I/O pin control block controls the communication mode (I2C bus or serial I/O mode), the number of pins used (two-line or three-line mode), and transmission or reception operation of serial interface 0. These control operations are performed by the serial I/O0 mode select register (refer to 19.5.1). 19.5.2 below shows the status of each pin set by the serial I/O0 mode select register. 19.5.1 Configuration and function of serial I/O0 mode select register (SIO0MODE)
Flag Symbol Name b3 S I O 0 C H b2 S B b1 S I O 0 M S b0 S I O 0 T X Address Read/ Write
Serial l/O0 mode select register (SIO1MODE)
08H
R/W
Sets serial I/O of P0A3/SDA pin in 2-line mode or P0A0/SO0 in 3-line mode (Selects "TX" or "RX") 2-line (P0A3/SDA pin) 0 1 Serial input (Hi-Z): RX operation Serial output : TX operation 3-line (P0A0/SO0 pin) General-purpose port Serial output : TX operation
Sets direction of shift clock I2C bus mode 0 1 Slave operation (external clock input) Master operation (internal clock output) Serial l/O mode External clock input Internal clock output
Selects pin used and communication mode 0 0 1 1 0 1 0 1 2-line serial I/O mode I2C bus mode 3-line serial l/O mode Setting prohibited
On reset
Power-ON Clock stop CE
0 0 0
0 0 0
0 0 0
0 0 0
19.5.2 Pin status set by serial I/O0 mode select register Table 19-2 shows the pin status set by the serial I/O0 mode select register. As shown in this table, the I/O select flag must be manipulated to set each pin. For the details of the I/O select flag, refer to 15. GENERAL-PURPOSE PORTS.
266
I
0
S
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------1 b2 B S 0 0
b3
O
H
C
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------2
SIO0MODE
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------Clock (slave) direction (master) External External External Internal Internal Internal
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------Input Input Output Serial I/O Output (reception) (reception) (transmission) (transmission)
1 0 1 0 cation mode I C bus 3-line 2-line Communiserial I/O serial I/O I 0 S O b1 M S 1 0 1 0 1 0 I 0 S T b0 O X 1 1 0 0 P0B3/SI0 P0B3/SI0 P0A0/SO0 P0A0/SO0 P0A2/SCL P0A2/SCL P0A3/SDA P0A2/SCL P0A3/SDA P0A3/SDA P0A1/SCK0 P0A1/SCK0 P0A1/SCK0 Pin symbol I A B P O 0 1 0 1 3 1 0 0 0 1 I 0 0 0 1 1 2 A B P O 1 0 0 1 0 I 1 0 1 A B P each pin O 0 I 0 0 A B P I/O select flag of O 0 I B B P O 3 Serial output External clock (Hi-Z) External clock (slave) General-purpose I/O port External clock Serial input (Hi-Z) General-purpose I/O port General-purpose I/O port General-purpose I/O port General-purpose I/O port General-purpose I/O port General-purpose I/O port General-purpose I/O port Internal clock Internal clock Set pin status Internal clock (master) Serial output (transmission) General-purpose output port General-purpose output port General-purpose output port General-purpose output port General-purpose output port Serial input (reception: Hi-Z)
1
1
0
Input
(reception)
Output
(transmission)
P0A0/SO0
P0B3/SI0
Table 19-2. Pin Status Set by Serial I/O0 Mode Select Register
Setting prohibited
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
1
1
Pin
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
1
0
0
1
0
General-purpose output port
Serial input
General-purpose input port
Serial output
PD17010
General-purpose output port
267
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19.6 Clock Generation Block
The clock generation block generates a clock when the internal clock is used (master operation) and controls the clock output timing. The internal clock frequency fSC is set by the serial I/O0 clock select register (refer to 19.6.1). The shift clock output by the clock generation block is valid only when the master operation (SIO0MS = 1) is performed. The shift clock is successively output, until serial communication is placed in the wait status because the wait condition described later is satisfied. 19.6.2 and 19.6.3 below describe the clock output waveform and generation timing in each communication mode. 19.6.1 Configuration and function of serial I/O0 clock select register (SIO0CLK)
Flag Symbol Name b3 S I Serial l/O0 clock select register (SIO0CLK) O 0 C K 3 b2 S I O 0 C K 2 b1 S I O 0 C K 1 b0 S I O 0 C K 0 39H R/W Address Read/ Write
Sets internal shift clock frequency fSC of serial interface 0 0 0 1 1 0 1 0 1 37.5 kHz 75 kHz 112.5 kHz 225 kHz
Fixed to "0"
On reset
Power-ON Clock stop CE
0
0 Undefined
Retained Retained
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19.6.2 Shift clock generation timing in I 2C bus mode (1) When wait status is released from initial status The "initial status" is the point at which the master operation in the I 2C bus mode has been selected. In the wait status, a low level is output to the shift clock pin (P0A2/SCL pin).
H Shift clock pin L 1/2fSC Wait status Initialization Wait released 1/fSC 1/2fSC
(2) When wait operation is performed For the details of the wait operation, refer to 19.9. (a) When wait status is set under condition of SIO0WRQ0 and SIO0WRQ1 flags (normal operation)
H Shift clock pin L Wait released status Wait period 1/fSC
Wait by SIO0WRQ1, Wait released SIO0WRQ0
(b) When forced wait status is set during wait status At this time, one pulse of the clock is output (however, the clock counter and presettable shift register 0 do not operate).
1/2fSC H Shift clock pin L Wait period Wait period
Forced wait by SIO0NWT
269
PD17010
(c) When forced wait status is set during wait release The wait status is set at the falling edge of the clock next to the one that has set the forced wait status. However, the clock counter and presettable shift register 0 stop operation when the forced wait status is set. If the forced wait status is set while the shift clock pin is low, the clock counter and presettable shift register operates for the duration of one pulse.
H Shift clock pin L Wait released status Wait pending Wait period Wait released 1/fSC
Forced wait by SIO0NWT H Shift clock pin L Wait released status Wait pending
Wait period Wait released
1/fSC
Forced wait by SIO0NWT
(d) If wait status is released during wait release Nothing is changed. (e) If wait request is issued by slave during wait release The clock is output 0 to 3.3 s after the wait request of the slave is cleared. * When master outputs low level
H Shift clock pin L Wait released status Wait period 1/fSC 0 to 3.3 s Wait request of slave Wait request of slave cleared
* When master outputs high level
H Shift clock pin L Wait released status T Wait period T 0 to 3.3 s Wait request of slave Wait request of slave cleared
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(3) Slave (external clock) operation When the slave operation is selected for the first time after application of supply voltage VDD, the output of the shift clock pin is undefined. If a low-level external clock is input when the shift clock pin is off (the actual pin level is high because the pin is externally pulled up), the shift clock pin retains the low level until the wait status is released. If a low-level external clock is not input, the shift clock pin retains the high level.
Note
H Shift clock pin L Undefined
External clock input (communication operation) Low-level external clock input Wait released Wait released Wait by SIO0WRQ1, SIO0WRQ0
Slave setting after application of VDD
Note When a low-level external clock is not input
271
PD17010
19.6.3 Shift clock generation timing in serial I/O mode (1) When wait status is released from initial status The "initial status" is the point at which the internal clock operation in the serial I/O mode has been selected. In the wait status, a high level is output to the shift clock pin (P0A2/SCL pin in the two-line mode and P0A1/ SCK0 pin in the three-line mode).
H Shift clock pin L 1/2fSC Wait status Initialization Wait released 1/fSC 1/2fSC
(2) When wait operation is performed For the details of the wait operation, refer to 19.9. (a) When wait status is set under condition of SIO0WRQ0 and SIO0WRQ1 flags (normal operation)
H Shift clock pin L Wait released status Wait period Wait released 1/fSC
Wait by SIO0WRQ1, SIO0WRQ0
(b) When forced wait status is set during wait status The shift clock pin retains the high level. However, note that the clock counter is reset.
H Shift clock pin L Wait period In wait status set by SIO0NWT, clock counter is reset Wait period
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(c) When forced wait status is set during wait release
T1 H Shift clock pin L Wait released status Forced wait by SIO0NWT Wait period Wait released 1/fSC - T1 T2 T1 + T2 = 1/2fSC
T1 H Shift clock pin L Wait released status Forced wait by SIO0NWT Wait period
T2 T1 + T2 = 1/2fSC
1/fSC - T1 Wait released
(d) If wait status is released during wait release The clock output waveform is not changed. However, note that the clock counter is reset.
19.7 Clock Counter and Start/Stop Detection Block
The clock counter is a wrap-around counter that counts the number of clocks input to the shift clock pin (P0A2/ SCL pin in the two-line mode and P0A1/SCK0 pin in the three-line mode) selected at that time. The clock counter directly reads the status of the shift clock pin. At this time, whether the clock is the internal clock or external clock is not judged. The clock counter does not operate in the wait status of serial communication. The contents of the clock counter can be detected via the SIO0SF8 and SIO0SF9 flags of the serial I/O0 status judge register, but cannot be directly read by program. The following 19.7.1 through 19.7.4 describe the configuration and function of the serial I/O0 status judge register, the operation of the clock counter, and how the clock counter is reset. The start/stop detection block detects the start/stop condition in the I2C bus mode. The start condition and stop condition can be detected by the SBSTT and SBBSY flags of the serial I/O0 status judge register. 19.7.5 describes the operations of the SBSTT and SBBSY flags.
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19.7.1 Configuration and function of serial I/O0 status judge register (SIO0STUS) The serial I/O0 status judge register detects the clock counter of serial interface 0 and the start/stop conditions in the I2C bus mode. The configuration and function of this register are illustrated below.
Flag Symbol Name b3 S I Serial l/O0 status judge register (SIO0STUS) O 0 S F 8 b2 S I O 0 S F 9 b1 S B S T T b0 S B B S Y 28H R Address Read/ Write
Detects start/stop conditions in I C bus mode I C bus mode 0 1 Reset to 0 when stop condition is detected Retains "0" Set to 1 when start condition is detected
2
2
Serial l/O mode
Detects start condition in I2C bus mode and clock counter I2C bus mode 0 1 Reset to 0 at falling edge of clock when clock counter is "9" Set to 1 when start condition is detected Serial l/O mode
Retains previous value
Detects clock counter of serial interface 0 0 1 Reset to 0 when clock counter is "0" or "1" Set to 1 when clock counter is "9"
Detects clock counter of serial interface 0 0 1 Reset to 0 when clock counter is "0" or "1" Set to 1 when clock counter is "8"
On reset
Power-ON Clock stop CE
0 0 0
0 0 0
0 0 0
0 0 0
274
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19.7.2 Operation of clock counter in I2C bus mode Figure 19-3 shows the operation of the clock counter. The initial value of the clock counter is "0". The clock counter is incremented each time the rising edge of the P0A2/ SCL pin has been detected. After its value has been incremented to "9", it is returned to "1" and the counter continues counting. The SIO0SF8 and SIO0SF9 flags detect the status in which the value of the clock counter reaches "8" and "9". These flags operate regardless of the master (internal clock) or slave (external clock), or the reception or transmission operation. Figure 19-3. Operation of Clock Counter in I2C Bus Mode
H Shift clock pin L H Serial data pin L D7 D6 D5 D1 D0 ACK 1 2 3 7 8 9
Clock counter 1 SIO0SF8 0 1 SIO0SF9 0
0
1
2
3
6
7
8
9
1
Wait released Clock counter reset
275
PD17010
19.7.3 Operation of clock counter in serial I/O mode Figure 19-4 shows the operation of the clock counter. The initial value of the clock counter is "0". The clock counter is incremented each time the rising edge of the shift clock pin has been detected. After its value has been incremented to "9", it is returned to "1" and the counter continues counting. The SIO0SF8 and SIO0SF9 flags detect the status in which the value of the clock counter reaches "8" and "9". These flags operate regardless of the master or slave, or the reception or transmission operation. Figure 19-4. Operation of Clock Counter in Serial I/O Mode
H Shift clock pin L H Serial data pin L D7 D6 D5 D1 D0 d7 1 2 3 7 8 9
Clock counter 1 SIO0SF8 0 1 SIO0SF9 0
0
1
2
3
6
7
8
9
1
Wait released Clock counter reset
19.7.4 Reset (0) condition of clock counter (1) In I 2C bus mode (a) On power-ON reset (b) On execution of clock stop instruction (c) On detection of start condition (d) If communication mode is changed from I 2C bus to 2- or 3-line serial I/O (e) On CE reset (2) In 2- or 3-line serial I/O mode (a) On power-ON reset (b) On execution of clock stop instruction (c) When data is written to serial I/O0 wait control register (d) If communication mode is changed from 2- or 3-line serial I/O to I 2C (e) On CE reset
276
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19.7.5 Operations of SBSTT and SBSSY flags Figure 19-5 shows the operations of the SBSTT and SBBSY flags. These flags operate only in the I2C bus mode. By detecting these flags, communication status of other stations can be detected. These flags operate regardless of whether the master or slave, or reception or transmission operation is performed, or whether the wait status is set or released. In the serial I/O mode, these flags retain "0". Figure 19-5. Operations of SBSTT and SBBSY Flags
Start condition 1 L H Serial data pin L D7 D6 D5 D1 D0 ACK 2 3 7 8 9 Stop condition
H Shift clock pin
Clock counter 1 SBSTT 0 1 SBBSY 0
0
1
2
3
6
7
8
9
1
The start and stop conditions are detected in the following timing (1) and (2). (1) Start condition detection timing
H Shift clock pin L H Serial data pin L 1.1 s Start condition is assumed if the shift clock pin is high 1.1 s after the low level of the serial data pin has been detected. Detects falling of serial data pin
(2) Stop condition detection timing
H Shift clock pin L H Serial data pin L 1.1 s Stop condition is assumed if the shift clock pin is high 1.1 s after the high level of the serial data pin has been detected. Detects rising of serial data pin
277
PD17010
19.8 Presettable Shift Register 0 (SIO0SFR)
The presettable shift register 0 is an 8-bit shift register that writes serial out data and reads serial in data. Data is written to or read from the presettable shift register 0 by the "PUT" or "GET" instruction via data buffer. 19.8.1 describes the configuration of the presettable shift register 0 and its relation with the data buffer. The data of the presettable shift register 0 is shifted in synchronization with the clock applied to the shift clock pin (P0A2/SCL pin in the two-line mode and P0A1/SCK0 pin in the three-line mode) selected at that time. In the I2C bus mode, the most significant bit (MSB) of the presettable shift register 0 is output to the serial data pin (P0A3/SDA pin) in synchronization with the falling edge of the shift clock, and the data of the serial data pin is read to the least significant bit (LSB) of the presettable shift register 0 in synchronization with the rising edge of the clock. 19.8.2 and 19.8.3 below describe the operation of the presettable shift register 0 in the I2C bus mode and serial I/O mode, and the points to be noted. 19.8.4 describes the points to be noted in writing or read data to or from the presettable shift register 0. The presettable shift register 0 does not shift data in the wait status. For the details of the operations of the register in the respective serial communication modes, refer to 19.11. 19.8.1 Configuration of presettable shift register 0 and its relation with data buffer The configuration of the presettable shift register 0 and its relation with the data buffer are illustrated below.
Name Symbol Address Bit Data b3
Data Buffer DBF3 0CH b2 b1 b0 b3 DBF2 0DH b2 b1 b0 b3 DBF1 0EH b2 b1 b0 b3 DBF0 0FH b2 b1 b0
Don't care
Don't care
Transfer data
8 Peripheral Register Name b7 M S B b6 b5 b4 b3 b2 b1 b0 L S B
GET can be executed PUT can be executed Symbol
Peripheral address Peripheral hardware
Presettable shift register 0
SIO0SFR
04H
Serial interface 0
Valid data
Setting of serial out data and reading serial in data D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Serial out Serial in
278
PD17010
19.8.2 Operation of presettable shift register in I2C bus mode Figure 19-6 shows the data shift operation in the I2C bus mode. Table 19-3 shows the data shift operation during reception or transmission in the I2C bus mode. Figure 19-6. Data Shift Operation in I2C Bus Mode
H Shift clock pin L Wait released Clock counter 0 1 2 3 6 7 8 9 10
1
2
6
7
8
9
1
H Serial data pin L D7 D6 D5 D2 D1 D0 ACK D7
b7 b6 b5 b4 b3 b2 b1 b0
D7 D6 D5 D4 D3 D2 D1 D0
D6 D5 D4 D3 D2 D1 D0 D7
D5 D4 D3 D2 D1 D0 D7 D6
D1 D0 D7 D6 D5 D4 D3 D2
D0 D7 D6 D5 D4 D3 D2 D1
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
Presettable shift register 0
SBACK flag
Table 19-3. Data Shift Operation during Reception and Transmission I2C Bus Mode Reception Transmission
Status of P0A3/SDA pin is input shifted Data is shifted from MSB and output to from LSB at rising edge of P0A2/SCL pin. P0A3/SDA pin at falling edge of P0A2/SCL No output is produced. pin. Content of SBACK flag is output at falling Status of P0A3/SDA pin is input from LSB edge of shift clock when clock counter is at rising edge of P0A2/SCL pin. "8". Does not operate in wait status. Status of P0A3/SDA pin is read to SBACK flag at rising edge of shift clock when clock counter reaches "9". Does not operate in wait status.
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19.8.3 Operation in serial I/O mode Figure 19-7 shows the data shift operation in the serial I/O mode. Table 19-4 shows the data shift operation during reception or transmission in the serial I/O mode. Figure 19-7. Data Shift Operation in Serial I/O Mode
H Shift clock pin L Wait released Clock counter 0 1 2 3 6 7 8 9 10
1
2
6
7
8
9
1
H Serial in pin L H Serial out pin L D7 D6 D5 D2 D1 D0 d7 d6 d7 d6 d5 d2 d1 d0 df de
b7 b6 b5 b4 b3 b2 b1 b0
D7 D6 D5 D4 D3 D2 D1 D0
D6 D5 D4 D3 D2 D1 D0 d7
D5 D4 D3 D2 D1 D0 d7 d6
D1 D0 d7 d6 d5 d4 d3 d2
D0 d7 d6 d5 d4 d3 d2 d1
d7 d6 d5 d4 d3 d2 d1 d0
d6 d5 d4 d3 d2 d1 d0 df
d5 d4 d3 d2 d1 d0 df de
Presettable shift register 0
Table 19-4. Data Shift Operation during Reception or Transmission Serial I/O Mode Reception Status of P0A3/SDA pin (P0B3/SI0 pin in 3line mode) is shifted from LSB and input at rising edge of shift clock pin. No output is produced. Does not operate in wait status. Transmission Data is shifted from MSB and output to P0A3/SDA pin (P0A0/SO0 pin in 3-line mode) at falling edge of shift clock. Status of P0A3/SDA (P0B3/SI0 in 3-line mode) pin is input from LSB at rising edge of shift clock. Does not operate in wait status.
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19.8.4 Notes on setting and reading data To set data to the presettable shift register 0, use the "PUT SIO0SFR, DBF" instruction. To read data, use the "GET DBF, SIO0SFR" instruction. Set or read data in the wait status. While the wait status is released, data may not be correctly set or read depending on the status of the shift clock pin. Table 19-5 shows the timing of setting and reading data, and points to be noted. Table 19-5. Reading (GET) and Writing (PUT) Data of Presettable Shift Register 0 and Notes
Status on Execution of PUT/GET Wait status Read (GET) Status of Shift Clock Pin I2C bus mode Fixed to low Normal read Normal write Outputs MSB contents as data when wait status is released next time (during transmission) Write (PUT) Serial I/O mode Fixed to high
PUT SIO0SFR, DBF Wait released PUT SIO0SFR, DBF Wait released Clock Data MSB Clock Data MSB
I2C Bus Mode
Serial I/O mode
Normal read Normal write Outputs MSB contents as data when wait status is released next time (during transmission)
Wait released status
Read (GET)
When low When high
Normal read Normal read (Set value is shifted 1 bit (MSB is shifted to LSB) and is read when internal clock is used)
Normal read Normal read (Set value is shifted 1 bit (MSB is shifted to LSB) and is read when internal clock is used) Normal write Outputs MSB contents at falling edge of shift clock. Clock counter is not reset.
Clock
Write (PUT)
When high
Normal write Outputs MSB contents at falling edge of shift clock. Clock counter is not reset.
Clock Data PUT SIO0SFR, DBF MSB
Data PUT SIO0SFR, DBF
MSB
When low
Cannot be written normally. Contents of SIO0SFR are lost
Cannot be written normally. Contents of SIO0SFR are lost
19.9 Wait Block and Acknowledge
The wait block places communication of serial interface 0 in the wait status or releases the wait status. The acknowledge block outputs and detects an acknowledge signal in the I2C bus mode. The wait block and acknowledge block are controlled by the serial I/O0 wait control register (refer to 19.9.1). The wait status is detected by the serial I/O0 wait status judge register (refer to 19.9.2). 19.9.3 through 19.9.5 describe the outline of the wait operation, wait operations in the respective communication modes, and points to be noted, and 19.9.6 describes the acknowledge block.
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19.9.1 Configuration and function of serial I/O0 wait control register (SIO0WT)
Flag Symbol Name b3 S B A C K b2 S I O 0 N W T b1 S I O 0 W R Q 1 b0 S I O 0 W R Q 0 Address Read/ Write
Serial l/O0 wait control register (SIO0WT)
18H
R/W
Sets wait condition Name 0 0 No wait I C bus mode Setting prohibited No wait
2
Serial l/O mode
0
1
Data wait
Wait at falling edge of shift clock when clock counter is "8"
Wait at rising edge of shift clock when clock counter is "8"
1
0
Acknowledge wait
Wait at falling edge of shift clock when clock counter is "9"
Wait at rising edge of shift clock when clock counter is "9"
1
1
Address wait
Wait at falling edge of shift clock when clock counter is "8" after start condition has been detected
Setting prohibited
Sets wait and detects wait status When writing to flag Forced wait
Releases wait (serial communication start)
When flag is read Wait in progress under condition of SIO0WRQ1 and 0 flags Serial communication in progress
0 1
Sets and detects acknowledge signal in I2C bus mode I C bus mode Serial l/O mode Reception (SIO0TX = 0) 0 Outputs "0" as acknowledge Transmission (SIO0TX = 1) Detects acknowledge of slave. Acknowledge is "0" Detects acknowledge of slave. Acknowledge is "1"
2
Does not operate. Therefore, can be used as 1-bit flag
1
Outputs "1" as acknowledge
On reset
Power-ON Clock stop CE
0 0 0
0 0 0
0 0 0
0 0 0
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19.9.2 Configuration and function of serial I/O0 wait status judge register (SIOWSTR)
Flag Symbol Name b3 b2 b1 b0 S I O Serial I/O0 wait status judge register (SIO0WSTR) 0 0 0 0 W S T T 19H R/W Address Read/ Write
Detects wait status of serial interface 0 0 1 * Wait under condition of SIO0WRQ1 and 0 flags * Wait by slave (master mode) Serial communication in progress
Fixed to "0"
On reset
Power-ON Clock stop CE
0
0
0
0 0 0
283
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19.9.3 Outline of wait operation In the wait status, the clock generation block and presettable shift register 0 stop operation, and therefore, serial communication stops. Serial communication can be executed by releasing the wait status. To release the wait status, write "1" to the SIO0NWT flag. When "1" is written to the SIO0NWT flag, the internal clock is output to the shift clock output pin (when the device is operating as the master), and the presettable shift register 0 and clock counter start operating. If the condition set by the SIO0WRQ0 and SIO0WRQ1 flags is satisfied, the wait status is set. At this time, the SIO0NWT flag is automatically reset to 0. By detecting the content of the SIO0NWT flag when the wait status has been released, the operation status of serial communication can be checked. Therefore, by writing "1" to the SIO0NWT flag and then detecting "0" of the SIO0NWT flag after serial communication has been started, data is read or set. Note that there is a time lag since the SIO0NWT flag has been cleared to "0" until the wait status is actually set. If data is set to the presettable shift register 0 (by using the PUT instruction) or data is read (by using the GET instruction) while the wait status is released, the correct data may not be set or read. For details, refer to 19.8. If "0" is written to the SIO0NWT flag while the wait status is released, the wait status is set. This is called "forced wait status". Note that there is a time lag for the forced wait status in the I2C bus mode since "0" has been written to the SIO0NWT flag until the wait status is actually set. If "0" is written to the SIO0NWT flag when the device operates as the master in the I2C bus mode, one pulse of the shift clock is output. Note that the clock counter and presettable shift register 0 stop operating at this time. If "1" is written to the SIO0NWT flag in the serial I/O mode, the clock counter is reset to 0. The wait status is detected by reading the contents of the SIO0WSTT flag. The SIO0WSTT flag is set to "1" also when the shift clock pin of the slave outputs a low level while the device is operating as the master. Because the SIO0WSTT flag is a read-only flag, it cannot be used to set or release the wait status, unlike the SIO0NWT flag.
284
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19.9.4 Wait operation and notes in I2C bus mode (1) Wait operation in I2C bus mode Figure 19-8 shows an example of the data wait (SIO0WRQ1 = 0, SIO0WRQ0 = 1) operation in the I2C bus mode. Figure 19-8. Data Wait Operation in I2C Bus Mode
H Shift clock pin L H Serial data pin L Clock counter Wait status 0 1 2 6 Wait release status 7 8 Wait status D7 D6 D5 D1 D0 ACK 1 2 3 7 8
Wait release and wait condition (data wait) setting
Wait by wait condition
When the wait status is released, serial data is output (during transmission), and the wait status remains released until the condition set by the SIO0WRQ1 and SIO0WRQ0 flags is satisfied. When the wait condition is satisfied, the serial clock pin is made low, and the clock counter and presettable shift register 0 stop operation. If data is written to the presettable shift register 0 while the wait status is released and the shift clock pin is low, the correct data may not be set. If data is written to the presettable shift register 0 while the wait is released and the shift clock pin is high, the content of the MSB is output to the serial data output pin at the falling edge of the shift clock next to the one at which the "PUT" instruction was executed. If the forced wait status is set while the wait status is released, the wait status is set at the falling edge of the clock next to the one at which "0" was written to the SIO0NWT flag. Nothing is changed even if the forced wait status is released while the wait status is released. If the forced wait status is set in the wait status, one pulse of the shift clock is output. Do not set the data wait condition (SIO0WRQ1 = 0, SIO0WRQ0 = 1) successively in the I2C bus mode. If the data wait condition is set two times in succession and then the wait status is released, the wait status is set immediately when the wait status is released the second time. Therefore, a different wait condition must be set after the wait status of the data wait condition. When the I2C bus mode is used, there is a period in which the status of the SIO0NWT flag and the actual communication operation differ as described in (2) and (3) below.
285
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(2) Normal wait operation in I 2C bus mode In the I 2C bus mode, communication is placed in the wait status at the falling edge of the shift clock if the wait condition set by the SIO0WRQ1 and SIO0WRQ0 flags is satisfied. Figure 19-9 shows the data wait operation and SIO0NWT flag operation in the I2C bus mode. As shown in <1> in this figure, the SIO0NWT flag is reset to "0" at the rising edge half the clock before the wait status is set. Therefore, if data is written (PUT) or read (GET) immediately after the SIO0NWT flag has been cleared to "0", the data may be lost. Consequently, write or read data after the low level of the shift clock pin has been detected after "0" was read from the SIO0NWT flag. Figure 19-9. Data Wait and SIO0NWT Flag Operations in I2C Bus Mode
H Shift clock pin L H Serial data pin L Clock counter 1 SIO0NWT flag 0 Wait status Wait released status <1> 0 1 2 3 6 7 8 Data must not be written or read during this period. Wait status D7 D6 D5 D1 D0 ACK 1 2 3 7 8 9
Wait released and setting of wait condition (data wait)
Wait by wait condition
(3) Forced wait operation in I 2C bus mode If "0" is written to the SIO0NWT flag while the wait status is released in the I 2C bus mode, the forced wait status is set at the falling edge of the next clock. Therefore, data must be written or read after the negative transition of the shift clock pin (from high to low) has been detected in the same manner as (1) above. If the forced wait status is set in the wait status while the device is operating as the master and receiving data, one pulse of the shift clock is output. This must be noted when setting the acknowledge signal described in 19.9.6. (4) Wait request by slave If the shift clock pin is forcibly made low by an external source (this is called wait request by a slave) while the pin is outputting a high level and while the device is operating as the master, the SIO0NWT flag is reset to "0". At this time, the SIO0NWT flag is set to 1 when the wait request by the slave has been released, and the device continues operation.
286
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19.9.5 Wait operation and note in serial I/O mode (1) Wait operation in serial I/O mode Figure 19-10 shows an example of the data wait (SIO0WRQ1 = 0, SIO0WRQ0 = 1) operation in the serial I/O mode. Figure 19-10. Data Wait Operation in Serial I/O Mode
H Shift clock pin L H Serial data pin L D7 D6 D5 D1 D0 1 2 3 7 8
Clock counter Wait status
0
1
2
3
6
7
8 Wait status
Wait released status
Wait release and wait condition (data wait) setting 1 SIO0NWT flag 0
Wait by wait condition
When the wait status is released, serial data is output at the next falling edge of the clock (during transmission operation), and the wait status is released until the condition set by the SIO0WRQ1 and SIO0WRQ0 flags is satisfied. When the wait condition is satisfied, the shift clock pin is made high, and the operations of the clock counter and presettable shift register 0 are stopped. If data is written to the presettable shift register 0 while the wait status is released and the shift clock pin is low, the correct data may not be set. If data is written to the presettable shift register 0 while the wait status is released and the shift clock pin is high, the content of the MSB is output to the serial data output pin at the next falling edge of the shift clock after the "PUT" instruction was executed. If the forced wait status is set in the wait status, the wait status is set immediately when "0" has been written to the SIO0NWT flag. If the wait status is released again while the wait status is released, the clock counter may be reset.
287
PD17010
19.9.6 Acknowledge block and its operation The acknowledge block operates only in the I2C bus mode. This block is used to output an acknowledge signal during the reception operation in the I2C bus mode, and to detect the acknowledge signal during transmission operation. During reception, the content of the SBACK flag is output to the serial data pin at the falling edge of the shift clock when the current value of the clock counter is "8" (the serial data pin automatically enters the output port). Once data has been set to the SBACK flag during reception, the value of the data is retained. During transmission, the status of the serial data pin is read to the SBACK flag at the rising edge of the shift clock when the current value of the clock counter is "9" (the serial data pin automatically enters the input port). Figure 19-11 illustrates the acknowledge signal output and input operations. Set the acknowledge signal (setting of the SBACK flag) during reception as soon as the wait status has been released (setting of SIO0NWT flag). This is because, even if an attempt is made to set the SBACK flag alone, the SIO0NWT flag is also set because the SIO0NWT flag is in the register at the same address. If the wait status is set at this time, the wait status is released and one pulse of the shift clock is output. In the serial I/O mode, the SBACK flag can be used as 1-bit general-purpose flag. Figure 19-11. Acknowledge Signal Output and Input Operations (1) Output operation (during reception)
H Shift clock pin L H Serial data pin L D1 D0
Content of SBACK flag
7
8
9
Clock counter
6
7
8
9
Data input
Acknowledge output. At this time, wait status must be released at the same time. l/O change
(2) Input operation (during transmission)
H Shift clock pin L H Serial data pin L D1 D0 Note D0 7 8 9
Clock counter
6
7
8
9
Data input
Read to SBACK flag I/O change
Note
Acknowledge signal from reception side the falling edge of the eighth clock.
Caution When the acknowledge signal is output or input, be sure to set the acknowledge wait status at
288
PD17010
19.10 Interrupt Control Block
The interrupt control block issues the interrupt request of serial interface 0 and sets the condition under which the interrupt request is to be issued by using the serial I/O0 interrupt mode register. When the interrupt request issuance condition is satisfied, the IRQSIO0 flag of the serial I/O0 interrupt request register (IREQSIO0: RF address 3BH) is set to 1. The following 19.10.1 describes the configuration and function of the serial I/O0 interrupt mode register. 19.10.2 and 19.10.3 indicate the interrupt request issuance timing in the respective communication modes. 19.10.1 Configuration and function of serial interface 0 interrupt mode register (SIO0INT) The functions of the respective flags of the serial interface 0 interrupt mode register is shown below. Do not change the contents of these flags during serial communication (when the SIO0NWT flag is "1"). Change these flags after "0" has been written to the SIO0NWT flag or when the SIO0NWT flag is "0". If the contents of these flags are changed during serial communication, an interrupt request may be issued as soon as the flag contents have been changed.
Flag Symbol Name b3 S I O Serial l/O0 interrupt mode register 0 I (SIO0INT) M D 3 b2 S I O 0 I M D 2 b1 S I O 0 I M D 1 b0 S I O 0 I M D 0 Address Read/ Write
38H
R/W
Sets interrupt request issuance condition I C bus mode 0 0 Rising of shift clock when clock counter reaches "7" Rising of shift clock when clock counter reaches "8"
2
Serial l/O mode Rising of shift clock when clock counter Note1 reaches "7" Rising of shift clock when clock counter Note2 reaches "8"
0
1
1
0
Rising of shift clock when clock counter reaches "7" after start condition has been Note3 detected When stop condition is detected
Note4
Interrupt request is not issued
1
1
Interrupt request is not issued
Fixed to "0"
On reset
Power-ON Clock stop CE
0
0 Undefined
Retained Retained
Notes 1. If this mode is set when the current value of the clock counter is "7", the interrupt request is issued. 2. If this mode is set when the current value of the clock counter is "8", the interrupt request is issued. 3. If this mode is selected when the SBSTT flag is "1" and the current value of the clock counter is "7", the interrupt request is issued. 4. When this mode is selected after the stop condition has been detected, the interrupt request is issued.
289
PD17010
19.10.2 Interrupt request issuance timing in I2C bus mode Figure 19-12 shows the interrupt request issuance timing in the I2C bus mode. Figure 19-12. Interrupt Request Issuance timing in I2C Bus Mode
Start condition 1 L H Serial data pin L D7 D6 D5 D1 D0 ACK 2 3 7 8 9 Stop condition
H Shift clock pin
Clock counter 1 SIO0SF8 0 1 SIO0SF9 0 1 SBSTT 0 1 SBBSY 0
0
1
2
3
6
7
8
9
1
Wait released Start condition
Wait condition Interrupt request issue timing
19.10.3 Interrupt request issuance timing in serial I/O mode Figure 19-13 shows the interrupt request issuance timing in the serial I/O mode. Figure 19-13. Interrupt Request Issuance Timing in Serial I/O Mode
H Shift clock pin L H Serial data pin L D7 D6 D5 D2 D1 D0 Df 1 2 3 6 7 8 9
Clock counter
0
1
2
3
5
6
7
8
9
1
1 SIO0SF8 0 1 SIO0SF9 0
Wait released Initialization
Wait condition
Interrupt request issue timing
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PD17010
19.11 Using Serial Interface 0
19.11.1 Using I 2C bus mode The I2C bus mode is selected by resetting the SIO0CH flag to "0" and setting the SB flag to "1". In this mode, the P0A3/SDA and P0A2/SCL pins are used. Figure 19-14 shows the I/O block and communication method in the I2C bus mode. Table 19-6 shows the pins used in the I2C bus mode and the function and operation of the control register. As shown in Figure 19-14 and Table 19-6, a master or slave operation can be performed in the I2C bus mode. Data can be transmitted (TX) or received (RX) during master and slave operations. The master or slave operation is selected by the SIO0MS flag, and the reception or transmission is selected by the SIO0TX flag. During the master operation, the internal shift clock is output from the P0A2/SCL pin. If transmission is carried out at this time, data is output from the P0A3/SDA pin at the falling edge of the shift clock. During reception, the status of the P0A3/SDA pin is input to the presettable shift register 0 at the rising edge of the shift clock. During master or slave operation, the start and stop conditions of serial communication can be detected by the SBSTT and SBBSY flags. The start and stop conditions are usually output by the master. This output is made by program (by controlling each pin as a general-purpose output port pin). During the slave operation, the P0A2/SCL pin is floated and the device waits for an external clock. If transmission is performed at this time, data is output from the P0A3/SDA pin at the falling edge of the shift clock. If reception is performed, the status of the P0A3/SDA pin is input to the presettable shift register 0 at the rising edge of the clock applied to the P0A2/SCL pin. During reception by the master or slave, an acknowledge signal is output each time 8-bit data has been communicated. During transmission by the master or slave, an acknowledge signal is detected each time 8-bit data has been communicated. The P0A3/SDA and P0A2/SCL pins are N-ch open-drain output pins; therefore, the communication line goes low if either the master or slave outputs a low level. When the values output to the P0A3/SDA and P0A2/SCL pins are read, the "status of pin at that time" is read. Paragraphs (1) through (4) below Table 19-6 show program examples for transmission and reception during master and slave operations.
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Figure 19-14. I/O Block and Communication Method in I2C Bus Mode I/O block
VDD
P0A2/SCL I/O control block P0ABIO2 SIO0MS
Wait signal
Shift clock output P0A2/SCL N-ch 1 0 1 0
P0A2 output latch
WRITE Port register READ Shift clock input
P0A3/SDA I/O control block P0ABIO3 SIO0TX
Serial data output P0A3/SDA N-ch 1 0 1 0
P0A3 output latch
WRITE Port register READ Serial data input
Communication method
H SDA pin L H SCL pin L Start condition Software control Wait released 1 2 Data read Data output Hardware control 3 7 8 9 Acknowledge Software setting Hardware control Stop condition Software control D7 D6 D1 D0 ACK
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Table 19-6. Outline of Operation in I2C Bus Mode
Operation Mode I2C Bus Mode SIO0CH=0, SB=1 Slave operation SIO0MS=0 Reception (RX) Transmission (TX) SIO0TX=0 SIO0TX=1 When P0ABIO3 = 0 Outputs contents of Floating SIO0SFR at falling External data input wait edge of external clock When P0ABIO3 = 1 regardless of P0ABIO3 General-purpose output port Outputs contents of output latch. Normally, P0ABIO3 is reset to 0. When P0ABIO2 = 0 When P0ABIO2 = 0 Floating Floating External clock input External clock input wait wait When P0ABIO2 = 1 When P0ABIO2 = 1 General-purpose out- General-purpose output port put port Outputs contents of Outputs contents of output latch. output latch. Normally, P0ABIO2 is Normally, P0ABIO2 is reset to 0. reset to 0. Incremented at rising edge of SCL pin Output Output Shifts data from MSB Not output and outputs it to SDA each time SCL pin falls Input Input Shifts data of SDA pin Shifts data of SDA pin from LSB and inputs it from LSB and inputs it each time SCL pin rises each time SCL pin rises Master operation SIO0MS=1 Reception (RX) Transmission (TX) SIO0TX=0 SIO0TX=1 When P0ABIO3 = 0 Floating External data input wait When P0ABIO3 = 1 General-purpose output port Outputs contents of output latch. Normally, P0ABIO3 is reset to 0. Outputs internal shift clock regardless of P0ABIO2 Outputs contents of SIO0SFR at falling edge of internal shift clock regardless of P0ABIO3
Item Setting status of each pin
P0A3/SDA
P0A2/SCL
Outputs internal shift clock regardless of P0ABIO2
Clock counter operation Operation of presettable shift register 0 (SIO0SFR)
Output Not output
Input Shifts data of SDA pin from LSB and inputs it each time SCL pin rises
Output Shifts data from MSB and outputs it to SDA each time SCL pin falls Input Shifts data of SDA pin from LSB and inputs it each time SCL pin rises
Wait operation
Serial communication is started when "1" is written to SIO0NWT. SIO0NWT is reset to "0" under condition set by SIO0WRQ1 and SIO0WRQ0 When SIO0NWT = 0 When SIO0NWT = 0 When SIO0NWT = 0 When SIO0NWT = 0 Forcibly outputs low Forcibly outputs low Forcibly outputs low Forcibly outputs low level from SCL pin. level from SCL pin. level from SCL pin. level from SCL pin. SDA pin retains its staSDA pin retains its sta- SDA pin is floated. SDA pin is floated. tus. tus. When SIO0NWT = 1 When SIO0NWT = 1 When SIO0NWT = 1 When SIO0NWT = 1 Outputs internal shift Outputs internal shift Floats SCL pin and Floats SCL pin and clock from SCK pin. clock from SCL pin. waits for external clock waits for external clock SDA pin is floated and Outputs ccontents of input. input. SDA pin is floated and Outputs contents of data of SDA pin is in- SIO0SFR to SDA pin data of SDA pin is in- SIO0SFR to SDA pin put to SIO0SFR at ris- at falling edge of SCL pin. put to SIO0SFR at ris- at falling edge of SCL ing edge of SCL pin. pin. ing edge of SCL pin.
Acknowledge
Outputs contents of SBACK flag are from SDA pin at falling edge of SCL pin when clock counter is 8
Status of SDA pin is written to SBCK flag at rising edge of SCL pin when clock counter reaches 9
Outputs contents of SBACK flag are from SDA pin at falling edge of SCL pin when clock counter is 8
Status of SDA pin is written to SBCK flag at rising edge of SCL pin when clock counter reaches 9
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(1) Program example in I 2C bus mode (in master transmission mode) Example To transmit 1-byte data "96H" to device with slave address of "1010010B" SDA SCL FLG FLG P0A3 P0A2 P0ABIO3 P0ABIO2
SDABIO FLG SCLBIO FLG INIT: CLR4 SET2 SET2 CLR1 CLR1 MOV MOV PUT
SIO0CH, SB, SIO0MS, SIO0TX SDABIO, SCLBIO SDA, SCL SDA SCL DBF1, #0AH DBF0, #4 SIO0SFR, DBF ; I2C bus, master, transmission ; Sets slave address ; "0" of bit b0 indicates transmission ; Issues start bit by program
INITFLG NOT SIO0CH, SB, SIO0MS, SIO0TX CLR2 SIO0CK1, SIO0CK0 ; Clock cycle = 37.5 kHz ( 100 kHz)
INITFLG SBACK, SIO0NWT, NOT SIO0WRQ1, SIO0WRQ0 ; Releases wait ; Wait condition is falling of shift clock when clock counter is "8" LOOP1: SKT1 BR CALL MOV MOV PUT SIO0SF8 LOOP1 CLK_WAIT DBF1, #9 DBF0, #6 SIO0SFR, DBF ; Waits until SCL pin goes low ; Sets transmit data ; Waits for data
INITFLG SBACK, SIO0NWT, SIO0WRQ1, NOT SIO0WRQ0 ; Releases wait ; Wait condition is falling of shift clock when clock counter is "9" LOOP2: SKT1 BR CALL SKF1 BR SIO0SF9 LOOP2 CLK_WAIT SBACK INIT ; Waits until SCL pin goes low ; Detects acknowledge ; Redoes if NACK ; Waits for acknowledge
INITFLG SBACK, SIO0NWT, NOT SIO0WRQ1, SIO0WRQ0 ; Releases wait ; Wait condition is falling edge of shift clock when clock counter is "8"
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LOOP3: SKT1 BR CALL SIO0SF8 LOOP3 CLK_WAIT ; Waits until SCL pin goes low ; Waits for data
INITFLG SBACK, SIO0NWT, SIO0WRQ1, NOT SIO0WRQ0 ; Releases wait ; Wait condition is falling edge of shift clock when clock counter is "9" LOOP4: SKT1 BR CALL SKF1 BR CLR4 LOOP5: SET1 SKT1 BR SET1 CLK_WAIT: SKF1 BR RET ... (2) Program example in I 2C bus mode (master reception mode) Example To receive 2-byte data from device with slave address "1010010B" and stores the data at addresses 00H through 03H of BANK0 SDA SCL FLG FLG P0A3 P0A2 P0ABIO3 P0ABIO2 0.00H 0.01H 0.02H 0.03H ; Stores higher 4 bits of first byte ; Stores lower 4 bits of first byte ; Stores higher 4 bits of second byte ; Stores lower 4 bits of second byte SDABIO FLG SCLBIO FLG DATA1H MEM DATA1L MEM DATA2H MEM DATA2L MEM SCL CLK_WAIT ... ; Subroutine SCL SCL LOOP5 SDA ; Issues stop bit by program SIO0SF9 LOOP4 CLK_WAIT SBACK INIT SIO0CH, SB, SIO0MS, SIO0TX ; Waits until SCL pin goes low ; Detects acknowledge ; Redoes if NACK ; Waits for acknowledge
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INIT: CLR4 SET2 SET2 CLR1 CLR1 MOV MOV PUT SIO0CH, SB, SIO0MS, SIO0TX SDABIO, SCLBIO SDA, SCL SDA SCL DBF1, #0AH DBF0, #5 SIO1SFR, DBF ; I2C bus, master, transmission CLR2 SIO0CK1, SIO0CK0 ; Clock cycle = 75 kHz ( 100 kHz) INITFLG SBACK, SIO0NWT, NOT SIO0WRQ1, SIO0WRQ0 ; Releases wait ; Wait condition is falling edge of shift clock when clock counter is "8" LOOP1: SKT1 BR CALL SIO0SF8 LOOP1 CLK_WAIT ; Waits until SCL pin goes low ; Waits for data ; Sets slave address ; "1" of bit b0 indicates reception ; Issues start bit by program
INITFLG NOT SIO0CH, SB, SIO0MS, SIO0TX
INITFLG SBACK, SIO0NWT, SIO0WRQ1, NOT SIO0WRQ0 ; Releases wait ; Wait condition is falling edge of shift clock when clock counter is "9" LOOP2: SKT1 BR CALL SKF1 BR CLR1 SIO0SF9 LOOP2 CLK_WAIT SBACK INIT SDABIO ; Sets SDA pin in input (reception) mode ; I2C bus, master, reception INITFLG SBACK, SIO0NWT, NOT SIO0WRQ1, SIO0WRQ0 ; Releases wait ; Wait condition is falling edge of shift clock when clock counter "8" ; Waits until SCL pin goes low ; Detects acknowledge ; Waits for acknowledge
INITFLG NOT SIO0CH, SB, SIO0MS, NOT SIO0TX
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LOOP3: SKT1 BR CALL SET1 GET ST ST SIO0SF8 LOOP3 CLK_WAIT SDABIO DBF, SIO0SFR DATA1H, DBF1 DATA1L, DBF0 ; Waits until SCL pin goes low ; Sets SDA pin in output (acknowledge output) mode ; Reads receive data ; Stores read data ; Waits for data
INITFLG NOT SBACK, SIO0NWT, SIO0WRQ1, NOT SIO0WRQ0 ; Outputs ACK (low level) ; Releases wait ; Wait condition is falling edge of shift clock when clock counter is "9" LOOP4: SKT1 BR CALL CLR1 SIO0SF9 LOOP4 CLK_WAIT SDABIO ; Waits until SCL pin goes low ; Sets SDA pin in input (data reception) mode ; Waits for acknowledge
INITFLG SBACK, SIO0NWT, NOT SIO0WRQ1, SIO0WRQ0 ; Releases wait ; Wait condition is falling edge of shift clock when clock counter is "8" LOOP5: SKT1 BR CALL SET1 GET ST ST SIO0SF8 LOOP5 CLK_WAIT SDABIO DBF, SIO0SFR DATA2H, DBF1 DATA2L, DBF0 ; Waits until SCL pin goes low ; Sets SDA pin in output (acknowledge output) mode ; Reads receive data ; Stores read data ; Waits for data
INITFLG NOT SBACK, SIO0NWT, SIO0WRQ1, NOT SIO0WRQ0 ; Outputs ACK (low level) ; Releases wait ; Wait condition is falling edge of shift clock when clock counter is "9" LOOP6: SKT1 BR CALL CLR4 SIO0SF9 LOOP6 CLK_WAIT SIO0CH, SB, SIO0MS, SIO0TX ; Waits until SCL pin goes low ; Waits for acknowledge
297
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LOOP7: SET1 SKT1 BR SET1 CLK_WAIT: SKF1 BR RET ... (3) Program example in I 2C bus mode (in slave transmission mode) Example To transmit 2-byte data "96C3H" with slave address of "1010010B" SDA SCL FLG FLG P0A3 P0A2 P0ABIO3 P0ABIO2 0.00H.0 ; "1" if data cannot be received SDABIO FLG SCLBIO FLG NG INIT: CLR2 SCLBIO, SDABIO ; I2C bus, slave, reception INITFLG SBACK, SIO0NWT, SIO0WRQ1, SIO0WRQ0 ; Releases wait ; Wait condition is falling edge of shift clock when clock counter is "8" after start ; condition has been detected LOOP1: SKT1 BR SBSTT LOOP1 ; Waits until start bit is detected INITFLG NOT SIO0CH, SB, NOT SIO0MS, NOT SIO0TX FLG SCL CLK_WAIT ... ; Subroutine SCL SCL LOOP7 SDA ; Issues stop bit by program
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LOOP2: SKT1 BR CALL SET1 GET ST ST SET2 SUB SUB SKT1 BR MOV MOV PUT CLR1 CLR1 SIO0SF8 LOOP2 CLK_WAIT SDABIO DBF, SIO0SFR R1, DBF1 R0, DBF0 CMP, Z DBF1, #0AH DBF0, #5 Z NACK0 DBF1, #9 DBF0, #6 SIO0SFR, DBF NG SDA ; Slave address coincides ; Sends ACK signal ; Slave address does not coincide ; Sets transmit data ; Detects coincidence of slave address ; If transmission/reception mode is set, ; does not judge bit b0 ; Waits until SCL pin goes low ; Sets SDA pin in output (acknowledge output) mode ; Reads slave address ; Waits for data
INITFLG NOT SBACK, SIO0NWT, SIO0WRQ1, NOT SIO0WRQ0 ; Outputs ACK (low level) ; Releases wait ; Wait condition is falling edge of shift clock when clock counter is "9" BR NACK0: SET1 SET1 NG SDA ; Slave address does not coincide ; Sends NACK signal LOOP3
INITFLG SBACK, SIO0NWT, SIO0WRQ1, NOT SIO0WRQ0 ; Outputs NACK (high level) ; Releases wait ; Wait condition is falling edge of shift clock when clock counter is "9" LOOP3: SKT1 BR CALL CLR1 SKF1 BR SIO0SF9 LOOP3 CLK_WAIT SDABIO NG INIT ; Redoes if slave address does not coincide ; I2C bus, slave, transmission INITFLG SBACK, SIO0NWT, NOT SIO0WRQ1, SIO0WRQ0 ; Releases wait ; Wait condition is falling edge of shift clock when clock counter is "8" ; Waits until SCL pin goes low ; Sets SDA pin in input (data reception) mode ; Waits for acknowledge
INITFLG NOT SIO0CH, SB, NOT SIO0MS, SIO0TX
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LOOP4: SKT1 BR CALL MOV MOV PUT SIO0SF8 LOOP4 CLK_WAIT DBF1, #0CH DBF0, #3 SIO0SFR, DBF ; Waits until SCL pin goes low ; Sets transmit data ; Waits for data
INITFLG NOT SBACK, SIO0NWT, SIO0WRQ1, NOT SIO0WRQ0 ; Releases wait ; Wait condition is falling edge of shift clock when clock counter is "9" LOOP5: SKT1 BR CALL SKF1 BR SIO0SF9 LOOP5 CLK_WAIT SBACK INIT ; Waits until SCL pin goes low ; Waits for acknowledge
INITFLG SBACK, SIO0NWT, NOT SIO0WRQ1, SIO0WRQ0 ; Releases wait ; Wait condition is falling edge of shift clock when clock counter is "8" LOOP6: SKT1 BR CALL SIO0SF8 LOOP6 CLK_WAIT ; Waits until SCL pin goes low ; Waits for data
INITFLG NOT SBACK, SIO0NWT, SIO0WRQ1, NOT SIO0WRQ0 ; Releases wait ; Wait condition is falling edge of shift clock when clock counter is "9" LOOP7: SKT1 BR CALL SKF1 BR SIO0SF9 LOOP7 CLK_WAIT SBACK INIT ; I2C bus, slave, reception INITFLG NOT SBACK, SIO0NWT, NOT SIO0WRQ1, SIO0WRQ0 ; Releases wait ; Wait condition is falling edge of shift clock when clock counter is "8" ; Waits until SCL pin goes low ; Waits for acknowledge
INITFLG NOT SIO0CH, SB, NOT SIO0MS, NOT SIO0TX
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LOOP8: SKF1 BR CLR4 CLK_WAIT: SKF1 BR RET ... (4) Program example in I 2C bus mode (slave reception mode) Example To receive 1-byte data from master and store it addresses 00H and 01H of BANK0. Slave address is "1010010B". SDA SCL FLG FLG P0A3 P0A2 P0ABIO3 P0ABIO2 0.00H 0.01H 0.02H.0 ; Stores higher 4 bits ; Stores lower 4 bits ; "0" if data is not received SDABIO FLG SCLBIO FLG DATAH DATAL NG INIT: INITFLG NOT SIO0CH, SB, NOT SIO0MS, NOT SIO0TX ; I2C bus, slave, reception INITFLG SBACK, SIO0NWT, SIO0WRQ1, SIO0WRQ0 ; Releases wait ; Wait condition is falling edge of shift clock when clock counter is "8" LOOP1: SKT1 BR SBSTT LOOP1 ; Waits until start bit is detected MEM MEM FLG SCL CLK_WAIT ... ; Subroutine SBBSY LOOP8 SIO0CH, SB, SIO0MS, SIO0TX ; Waits until stop bit is detected
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LOOP2: SKT1 BR CALL SET1 GET SKNE SKE BR CLR1 CLR1 SIO0SF8 LOOP2 CLK_WAIT SDABIO DBF, SIO0SFR DBF1, #0AH DBF0, #4 NACK0 NG SDA ; Waits until SCL pin goes low ; Sets SDA pin in output (acknowledge output) mode ; Reads slave address ; Detects coincidence of slave address ; CMP flag may be used ; Slave address does not coincide ; Slave address coincides ; Sends ACK signal ; Waits for data
INITFLG NOT SBACK, SIO0NWT, SIO0WRQ1, NOT SIO0WRQ0 ; Outputs ACK (low level) ; Releases wait ; Wait condition is falling edge of shift clock when clock counter is "9" BR NACK0: SET1 SET1 NG SDA ; Slave address does not coincide ; Sends NACK signal LOOP3
INITFLG SBACK, SIO0NWT, SIO0WRQ1, NOT SIO0WRQ0 ; Outputs NACK (high level) ; Releases wait ; Wait condition is falling edge of shift clock when clock counter is "9" LOOP3: SKT1 BR CALL CLR1 SKF1 BR SIO0SF9 LOOP3 CLK_WAIT SDABIO NG INIT ; Redoes if slave address does not coincide ; Waits until SCL pin goes low ; Sets SDA pin in input (data reception) mode ; Waits for acknowledge
INITFLG SBACK, SIO0NWT, NOT SIO0WRQ1, SIO0WRQ0 ; Releases wait ; Wait condition is falling edge of shift clock when clock counter is "8"
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LOOP4: SKT1 BR CALL SET1 GET ST ST CLR1 SIO0SF8 LOOP4 CLK_WAIT SDABIO DBF, SIO0SFR DATAH, DBF1 DATAL, DBF0 SDA ; Sends ACK signal ; Waits until SCL pin goes low ; Sets SDA pin in output (acknowledge output) mode ; Reads receive data ; Stores read data ; Waits for data
INITFLG NOT SBACK, SIO0NWT, SIO0WRQ1, NOT SIO0WRQ0 ; Outputs ACK (low level) ; Releases wait ; Wait condition is falling edge of shift clock when clock counter is "9" LOOP5: SKT1 BR CALL CLR1 SIO0SF9 LOOP5 CLK_WAIT SDABIO ; Waits until SCL pin goes low ; Waits for acknowledge
INITFLG NOT SBACK, SIO0NWT, NOT SIO0WRQ1, SIO0WRQ0 ; Releases wait ; Wait condition is falling edge of shift clock when clock counter is "8" LOOP6: SKF1 BR CLR4 CLK_WAIT: SKF1 BR RET ... SCL CLK_WAIT ... ; Subroutine SBBSY LOOP6 SIO0CH, SB, SIO0MS, SIO0TX ; Waits until stop bit is detected
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19.11.2 Using 2-line serial I/O mode The two-line serial I/O mode is selected by resetting both the SIO0CH and SB flags to "0". In this mode, the P0A3/SDA and P0A2/SCL pins are used. Figure 19-15 shows the I/O block and communication method in the two-line serial I/O mode. Table 19-7 shows the functions and operations of the respective pins and control register in the two-line serial I/O mode. As shown in Figure 19-15 and Table 19-7, an internal clock (master) and external clock (slave) operation may be performed in the two-line serial I/O mode. Data can be transmitted (TX) or received (RX) in both the master and slave modes. The master or slave operation is selected by the SIO0MS flag, and reception or transmission is selected by the SIO0TX flag. During the master operation, the internal shift clock is output from the P0A2/SCL pin. If transmission is performed at this time, data is output from the P0A3/SDA pin at the falling edge of the shift clock. If reception is performed, the status of the P0A3/SDA pin is input to the presettable shift register 0 at the rising edge of the shift clock. During the slave operation, the P0A2/SCL pin is floated (Hi-Z state), and the device waits for an external clock. If transmission is performed at this time, data is output from the P0A3/SDA pin at the falling edge of the shift clock. If reception is performed, the status of the P0A3/SDA pin is input to the presettable shift register 0 at the rising edge of the clock applied to the P0A2/SCL pin. The P0A3/SDA and P0A2/SCL pins are N-ch open-drain output pins; therefore, the communication line goes low if either the master or slave outputs a low level. When the values output to the P0A3/SDA and P0A2/SCL pins are read, the "status of pin at that time" is read. Paragraphs (1) through (4) below Table 19-7 show program examples for transmission and reception during master and slave operations.
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Figure 19-15. I/O Block and Communication Method in 2-Line Serial Mode I/O block
VDD
P0A2/SCL I/O control block P0ABIO2 SIO0MS
Wait signal
Shift clock output P0A2/SCL N-ch 1 0 1 0
P0A2 output latch
WRITE Port register READ Shift clock input
P0A3/SDA I/O control block P0ABIO3 SIO0TX
Serial data output P0A3/SDA N-ch 1 0 1 0
P0A3 output latch
WRITE Port register READ Serial data input
Communication method
H SDA pin L H SCL pin L Data read Data output Hardware control Wait released Wait status 1 2 3 7 8 D7 D6 D1 D0
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Table 19-7. Outline of Operation in 2-Line Serial I/O Mode
Operation Mode 2-line Serial I/O Mode SIO0CH=0, SB=0 Slave operation SIO0MS=0 Reception (RX) Transmission (TX) SIO0TX=0 SIO0TX=1 P0A3/SDA When P0ABIO3 = 0 Outputs contents of Floating SIO0SFR at falling External data input wait edge of external clock When P0ABIO3 = 1 regardless of P0ABIO3 General-purpose output port Outputs contents of output latch. Normally, P0ABIO3 is reset to 0. When P0ABIO2 = 0 When P0ABIO2 = 0 Floating Floating External clock input External clock input wait wait When P0ABIO2 = 1 When P0ABIO2 = 1 General-purpose out- General-purpose output port put port Outputs contents of Outputs contents of output latch. output latch. Normally, P0ABIO2 is Normally, P0ABIO2 is reset to 0. reset to 0. Incremented at rising edge of SCL pin Output Output Shifts data from MSB Not output and outputs it to SDA each time SCL pin falls Input Input Shifts data of SDA pin Shifts data of SDA pin from LSB and inputs it from LSB and inputs it each time SCL pin rises each time SCL pin rises Master operation SIO0MS=1 Reception (RX) Transmission (TX) SIO0TX=0 SIO0TX=1 When P0ABIO3 = 0 Floating External data input wait When P0ABIO3 = 1 General-purpose output port Outputs contents of output latch. Normally, P0ABIO3 is reset to 0. Outputs internal shift clock regardless of P0ABIO2 Outputs contents of SIO0SFR at falling edge of internal shift clock regardless of P0ABIO3
Item Setting status of each pin
P0A2/SCL
Outputs internal shift clock regardless of P0ABIO2
Clock counter operation Operation of presettable shift register 0 (SIO0SFR)
Output Not output
Input Shifts data of SDA pin from LSB and inputs it each time SCL pin rises
Output Shifts data from MSB and outputs it to SDA each time SCL pin falls Input Shifts data of SDA pin from LSB and inputs it each time SCL pin rises
Wait operation
Serial communication is started when "1" is written to SIO0NWT. SIO0NWT is reset to "0" under condition set by SIO0WRQ1 and SIO0WRQ0 When SIO0NWT = 0 When SIO0NWT = 0 When SIO0NWT = 0 When SIO0NWT = 0 SCL pin is floated. SCL pin is floated. SCL pin is floated. SCL pin is floated. SDA pin is floated. SDA pin retains its sta- SDA pin is floated. SDA pin retains its status. tus. When SIO0NWT = 1 When SIO0NWT = 1 When SIO0NWT = 1 When SIO0NWT=1 Floats SCL pin and Outputs internal shift Outputs internal shift Floats SCL pin and waits for external clock clock from SCL pin. clock from SCL pin. waits for external clock input. SDA pin is floated and Outputs contents of input. SDA pin is floated and data of SDA pin is in- SIO0SFR to SDA pin SDA pin is floated and data of SDA pin is input to SIO0SFR at ris- at falling edge of SCL data of SDA pin is input to SIO0SFR at rising edge of SCL pin. pin. put to SIO0SFR at falling edge of SCL pin. ing edge of SCL pin.
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(1) Program example in 2-line serial I/O mode (master transmission mode) Example To transmit 2-byte data "A596H" INITFLG NOT SIO0CH, NOT SB, SIO0MS, SIO0TX ; 2-line serial I/O, master, transmission CLR2 MOV MOV PUT SIO0CK1, SIO0CK0 DBF1, #0AH DBF0, #5 SIO0SFR, DBF ; Clock cycle = 37.5 kHz ; Sets first byte of transmit data
INITFLG NOT SBACK, SIO0NWT, NOT SIO0WRQ1, SIO0WRQ0 ; Releases wait ; Wait condition is rising edge of shift clock when clock counter is "8" LOOP1: SKF1 BR MOV MOV PUT SIO0NWT LOOP1 DBF1, #9 DBF0, #6 SIO0SFR, DBF ; Sets second byte of transmit data ; Waits until wait status is released
INITFLG NOT SBACK, SIO0NWT, NOT SIO0WRQ1, SIO0WRQ0 ; Releases wait ; Wait condition is rising edge of shift clock when clock counter is "8" LOOP2: SKF1 BR ... SIO0NWT LOOP2 ; Wait until wait status is released
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(2) Program example in 2-line serial I/O mode (master reception mode) Example To receive and store 2-byte data to addresses 00H through 03H of BANK0 SDABIO FLG DATA1H MEM DATA1L MEM DATA2H MEM DATA2L MEM CLR1 SDABIO ; 2-line serial I/O, master, transmission INITFLG NOT SIO0CK1, SIO0CK0 ; Releases wait ; Wait condition is rising edge of shift clock when clock counter is "8" LOOP1: SKF1 BR GET ST ST SIO0NWT LOOP1 DBF, SIO0SFR DATA1H, DBF1 DATA1L, DBF0 ; Reads receive data ; Stores read data ; Wait until wait status is released ; Clock cycle = 75 kHz INITFLG NOT SBACK, SIO0NWT, NOT SIO0WRQ1, SIO0WRQ0 P0ABIO3 0.00H 0.01H 0.02H 0.03H ; Stores higher 4 bits of first byte ; Stores lower 4 bits of first byte ; Stores higher 4 bits of second byte ; Stores lower 4 bits of second byte
INITFLG NOT SIO0CH, NOT SB, SIO0MS, NOT SIO0TX
INITFLG NOT SBACK, SIO0NWT, NOT SIO0WRQ1, SIO0WRQ0 ; Releases wait ; Wait condition is rising edge of shift clock when clock counter is "8" LOOP2: SKF1 BR GET ST ST ... SIO0NWT LOOP2 DBF, SIO0SFR DATA2H, DBF1 DATA2L, DBF0 ; Reads receive data ; Stores read data ; Waits until wait status is released
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(3) Program example in 2-line serial I/O mode (slave transmission mode) Example To transmit 2-byte data "A596H" SCLBIO FLG CLR1 SCLBIO ; 2-line serial I/O, slave, transmission MOV MOV PUT DBF1, #0AH DBF0, #5 SIO0SFR, DBF ; Sets transmit data P0ABIO2
INITFLG NOT SIO0CH, NOT SB, NOT SIO0MS, SIO0TX
INITFLG NOT SBACK, SIO0NWT, NOT SIO0WRQ1, SIO0WRQ0 ; Releases wait ; Wait condition is rising edge of shift clock when clock counter is "8" LOOP1: SKF1 BR MOV MOV PUT SIO0NWT LOOP1 DBF1, #9 DBF0, #6 SIO0SFR, DBF ; Sets transmit data ; Waits until wait status is released
INITFLG NOT SBACK, SIO0NWT, NOT SIO0WRQ1, SIO0WRQ0 ; Releases wait ; Wait condition is rising edge of shift clock when clock counter is "8" LOOP2: SKF1 BR ... SIO0NWT LOOP2 ; Waits until wait status is released
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(4) Program example in 2-line serial I/O mode (slave reception mode) Example To receive and store 2-byte data to addresses 00H through 03H of BANK0 SDABIO FLG SCLBIO FLG DATA1H MEM DATA1L MEM DATA2H MEM DATA2L MEM CLR2 CLR4 P0ABIO3 P0ABIO2 0.00H 0.01H 0.02H 0.03H ; Stores higher 4 bits of first byte ; Stores lower 4 bits of first byte ; Stores higher 4 bits of second byte ; Stores lower 4 bits of second byte
SCLBIO, SDABIO SIO0CH, SB, SIO0MS, SIO0TX ; 2-line serial I/O, slave, reception
INITFLG NOT SBACK, SIO0NWT, NOT SIO0WRQ1, SIO0WRQ0 ; Releases wait ; Wait condition is rising edge of shift clock when clock counter is "8" LOOP1: SKF1 BR GET ST ST SIO0NWT LOOP1 DBF, SIO0SFR DATA1H, DBF1 DATA1L, DBF0 ; Reads receive data ; Stores read data ; Waits until wait status is released
INITFLG NOT SBACK, SIO0NWT, NOT SIO0WRQ1, SIO0WRQ0 ; Releases wait ; Wait condition is rising edge of shift clock when clock counter is "8" LOOP2: SKF1 BR GET ST ST ... SIO0NWT LOOP2 DBF, SIO0SFR DATA2H, DBF1 DATA2L, DBF0 ; Reads receive data ; Stores read data ; Waits until wait status is released
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19.11.3 Using three-line serial I/O mode The three-line serial I/O mode is selected by setting the SIO0CH flag to "1" and resetting the SB flags to "0". In this mode, the P0A1/SCK0, P0A0/SO0, and P0B3/SI0 pins are used. Figure 19-16 shows the I/O block and communication method in the three-line serial I/O mode. Table 19-8 shows the functions and operations of the respective pins and control register in the three-line serial I/O mode. As shown in Figure 19-16 and Table 19-8, an internal clock (master) and external clock (slave) operation may be performed in the three-line serial I/O mode. Data can be transmitted (TX) or received (RX) in both the master and slave modes. The master or slave operation is selected by the SIO0MS flag, and reception or transmission is selected by the SIO0TX flag. During the master operation, the internal shift clock is output from the P0A1/SCK0 pin. If transmission is performed at this time, data is output from the P0A0/SO0 pin at the falling edge of the shift clock. During master operation, the status of the P0B3/SI0 pin is input to the presettable shift register 0 at the rising edge of the shift clock, regardless of whether transmission or reception is performed. At this time, however, the P0B3/SI0 pin must be set in this input mode. During the slave operation, the P0A1/SCK0 pin is floated (Hi-Z state), and the device waits for an external clock. If transmission is performed at this time, data is output from the P0A3/SDA pin at the falling edge of the shift clock. During slave operation, the status of the P0B3/SI0 pin is input to the presettable shift register 0 at the rising edge of the shift clock, regardless of whether transmission or reception is performed. However, the P0B3/SI0 pin must be set in the input mode. The "status of the output latch at that time" is read when the contents of the port register corresponding to the P0A1/ SCK0 or P0A0/SO0 pin are read. Paragraphs (1) through (4) below Table 19-8 show program examples for transmission and reception during master and slave operations.
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Figure 19-16. I/O Block and Communication Method in 3-Line Serial Mode (1/2) I/O block
Wait signal P0A1/SCK0 l/O control block P0ABIO1 VDD VDD 1 P-ch P0A1/SCK0 N-ch 0
P0A1 output latch
SIO0MS
Shift clock output WRITE Port register READ
Shift clock input
P0A0/SO0 l/O control block P0ABIO0 VDD VDD 1 P-ch P0A0/SO0 N-ch 0
P0A0 output latch
SIO0TX
Serial data output WRITE Port register READ
P0B3/SI0 l/O control block P0BBIO3
VDD
VDD P-ch P0B3/SI0 N-ch
P0B3 output latch
WRITE Port register READ Serial data input
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Figure 19-16. I/O Block and Communication Method in 3-Line Serial Mode (2/2) Communication method
H SI0 pin L H SO0 pin L H SCK0 pin L Data read Data output Hardware control Wait released Wait status 1 2 3 7 8 D7 D6 D1 D0 d7 d6 d1 d0
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Table 19-8. Outline of Operation in 3-Line Serial I/O Mode
Operation Mode 3-line Serial I/O Mode SIO0CH=1, SB=0 Slave operation SIO0MS=0 Reception (RX) Transmission (TX) SIO0TX=0 SIO0TX=1 P0A1/SCK0 Master operation SIO0MS=1 Reception (RX) Transmission (TX) SIO0TX=0 SIO0TX=1
Item Setting status of each pin
P0A0/SO0
P0B3/SI0
Clock counter operation Operation of presettable shift register 0 (SIO0SFR)
Wait operation
When P0ABIO1 = 0 When P0ABIO1 = 0 Internal shift clock is Internal shift clock is Floating Floating output regardless of output regardless of External clock input External clock input P0ABIO1 P0ABIO1 wait wait When P0ABIO1 = 1 When P0ABIO1 = 1 General-purpose out- General-purpose output port put port Outputs contents of Outputs contents of output latch. output latch. Normally, P0ABIO1 is Normally, P0ABIO1 is reset to 0. reset to 0. Outputs contents of When P0ABIO0 = 0 When P0ABIO0 = 0 Outputs contents of General-purpose input SIO0SFR at falling General-purpose input SIO0SFR at falling edge of external clock port port edge of internal shift regardless of P0ABIO0 Floating Floating clock regardless of When P0ABIO0 = 1 When P0ABIO0 = 1 P0ABIO0 General-purpose outGeneral-purpose output port put port Outputs contents of Outputs contents of output latch. output latch. When P0BBIO3 = 0 When P0BBIO3 = 0 When P0BBIO3 = 0 When P0BBIO3 = 0 Floating Floating Floating Floating External data input wait External data input wait External data input wait External data input wait When P0BBIO3 = 1 When P0BBIO3 = 1 When P0BBIO3 = 1 When P0BBIO3 = 1 General-purpose out- General-purpose out- General-purpose out- General-purpose output port put port put port put port Outputs contents of Outputs contents of Outputs contents of Outputs contents of output latch. output latch. output latch. output latch. Normally, P0BBIO3 is Normally, P0BBIO3 Normally, P0BBIO3 is Normally, P0BBIO3 is reset to 0. reset to 0. reset to 0. is reset to 0. Incremented at rising edge of SCK0 pin Output Output Output Output Not output Not output Shifts data from MSB Shifts data from MSB and outputs it to SO0 and outputs it to SO0 pin each time SCK0 pin pin each time SCK0 pin falls falls Input Input Input Input Shifts data of SI0 pin Shifts data of SI0 pin Shifts data of SI0 pin Shifts data of SI0 pin from LSB and inputs it from LSB and inputs it from LSB and inputs it from LSB and inputs it each time SCK0 pin each time SCK0 pin each time SCK0 pin each time SCK0 pin rises rises rises rises Serial communication is started when "1" is written to SIO0NWT. SIO0NWT is reset to "0" under condition set by SIO0WRQ1 and SIO0WRQ0 When SIO0NWT = 0 SCK0 pin is floated. SO0 pin is generalpurpose port. SI0 pin is floated. When SIO0NWT = 1 SCK0 pin waits for input of external clock. Inputs data of SI0 pin to SIO0SFR at rising edge of SCK0 pin. When SIO0NWT = 0 SCK0 pin is floated. SO0 pin retains its status. SI0 pin is floated. When SIO0NWT = 1 SCK0 pin waits for input of external clock. Outputs contents of SIO0SFR to SO0 pin at falling edge of SCK0 pin. Inputs data of SI0 pin to SIO0SFR at rising edge of SCK0 pin. When SIO0NWT = 0 SCK0 pin outputs high level. SO0 pin is generalpurpose port. SI0 pin is floated. When SIO0NWT = 1 SCK0 pin outputs internal shift clock. Inputs data of SI0 pin to SIO0SFR at rising edge of SCK0 pin. When SIO0NWT = 0 SCK0 pin outputs high level. SO0 pin retains its status. SI0 pin is floated. When SIO0NWT = 1 Outputs internal shift clock from SCK0 pin. Outputs contents of SIO0SFR to SO0 pin at falling edge of SCK0 pin. Inputs data of SI0 pin to SIO0SFR at rising edge of SCK0 pin.
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(1) Program example in 3-line serial I/O mode (master transmission mode) Example To transmit 2-byte data "A596H" INITFLG SIO0CH, NOT SB, SIO0MS, SIO0TX ; 3-line serial I/O, master, transmission INITFLG SIO0CK1, NOT SIO0CK0 MOV MOV PUT DBF1, #0AH DBF0, #5 SIO0SFR, DBF ; Clock cycle = 112.5 kHz ; Sets transmit data
INITFLG NOT SBACK, SIO0NWT, NOT SIO0WRQ1, SIO0WRQ0 ; Releases wait ; Wait condition is rising edge of shift clock when clock counter is "8" LOOP1: SKF1 BR MOV MOV PUT SIO0NWT LOOP1 DBF1, #9 DBF0, #6 SIO0SFR, DBF ; Sets transmit data ; Wait until wait status is released
INITFLG NOT SBACK, SIO0NWT, NOT SIO0WRQ1, SIO0WRQ0 ; Releases wait ; Wait condition is rising edge of shift clock when clock counter is "8" LOOP2: SKF1 BR ... SIO0NWT LOOP2 ; Waits until wait status is released
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(2) Program example in 3-line serial I/O mode (master reception mode) Example To receive and store 2-byte data to addresses 00H through 03H of BANK0 SI0BIO FLG P0BBIO3 0.00H 0.01H 0.02H 0.03H ; Stores higher 4 bits of first byte ; Stores lower 4 bits of first byte ; Stores higher 4 bits of second byte ; Stores lower 4 bits of second byte
DATA1H MEM DATA1L MEM DATA2H MEM DATA2L MEM CLR1 SI0BIO
INITFLG SIO0CH, NOT SB, SIO0MS, NOT SIO0TX ; 3-line serial I/O, master, reception SET2 SIO0CK1, SIO0CK0 ; Clock cycle = 225 kHz INITFLG NOT SBACK, SIO0NWT, NOT SIO0WRQ1, SIO0WRQ0 ; Releases wait ; Wait condition is rising edge of shift clock when clock counter is "8" LOOP1: SKF1 BR GET ST ST SIO0NWT LOOP1 DBF, SIO0SFR DATA1H, DBF1 DATA1L, DBF0 ; Reads receive data ; Stores read data ; Waits until wait status is released
INITFLG NOT SBACK, SIO0NWT, NOT SIO0WRQ1, SIO0WRQ0 ; Releases wait ; Wait condition is rising edge of shift clock when clock counter is "8" LOOP2: SKF1 BR GET ST ST ... SIO0NWT LOOP2 DBF, SIO0SFR DATA2H, DBF1 DATA2L, DBF0 ; Reads receive data ; Stores read data ; Waits until wait status is released
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(3) Program example in 3-line serial I/O mode (slave transmission mode) Example To transmit 2-byte data "A596H" SCK0BIO FLG CLR1 SCK0BIO ; 3-line serial I/O, slave, transmission MOV MOV PUT DBF1, #0AH DBF0, #5 SIO1SFR, DBF ; Sets transmit data P0ABIO1
INITFLG SIO0CH, NOT SB, NOT SIO0MS, SIO0TX
INITFLG NOT SBACK, SIO0NWT, NOT SIO0WRQ1, SIO0WRQ0 ; Releases wait ; Wait condition is rising edge of shift clock when clock counter is "8" LOOP1: SKF1 BR MOV MOV PUT SIO0NWT LOOP1 DBF1, #9 DBF0, #6 SIO0SFR, DBF ; Sets transmit data ; Waits until wait status is released
INITFLG NOT SBACK, SIO0NWT, NOT SIO0WRQ1, SIO0WRQ0 ; Releases wait ; Wait condition is rising edge of shift clock when clock counter is "8" LOOP2: SKF1 BR ... SIO0NWT LOOP2 ; Waits until wait status is released
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(4) Program example in 3-line serial I/O mode (slave reception mode) Example To receive and store 2-byte data to addresses 00H through 03H of BANK0 SCK0BIO FLG SI0BIO FLG P0ABIO1 P0BBIO3 0.00H 0.01H 0.02H 0.03H ; Stores higher 4 bits of first byte ; Stores lower 4 bits of first byte ; Stores higher 4 bits of second byte ; Stores lower 4 bits of second byte
DATA1H MEM DATA1L MEM DATA2H MEM DATA2L MEM CLR2
SCK0BIO, SI0BIO ; 3-line serial I/O, slave, reception
INITFLG SIO0CH, NOT SB, NOT SIO0MS, NOT SIO0TX INITFLG NOT SBACK, SIO0NWT, NOT SIO0WRQ1, SIO0WRQ0 ; Releases wait ; Wait condition is rising edge of shift clock when clock counter is "8" LOOP1: SKF1 BR GET ST ST SIO0NWT LOOP1 DBF, SIO0SFR DATA1H, DBF1 DATA1L, DBF0 ; Reads receive data ; Stores read data ; Waits until wait status is released
INITFLG NOT SBACK, SIO0NWT, NOT SIO0WRQ1, SIO0WRQ0 ; Releases wait ; Wait condition is rising edge of shift clock when clock counter is "8" LOOP2: SKF1 BR GET ST ST ... SIO0NWT LOOP2 DBF, SIO0SFR DATA2H, DBF1 DATA2L, DBF0 ; Reads receive data ; Stores read data ; Waits until wait status is released
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19.12 Reset Status of Serial Interface 0
19.12.1 At power-ON reset All the P0A3/SDA through P0A0/SO0 and P0B3/SI0 pins are set in the general-purpose input port mode (floating output). The value of the presettable shift register 0 is undefined. 19.12.2 On execution of clock stop instruction All the P0A3/SDA through P0A0/SO0 and P0B3/SI0 pins are set in the general-purpose input port mode (floating output). The presettable shift register 0 retains the previous value. 19.12.3 At CE reset All the P0A3/SDA through P0A0/SO0 and P0B3/SI0 pins are set in the general-purpose input port mode (floating output). The presettable shift register 0 retains the previous value. 19.12.4 In halt status The I/O pins retain the current status. If the internal clock is used (master operation) at this time, the clock is not output when the "HALT" instruction has been executed. Therefore, the "HALT" instruction must be executed after communication has been completed when the internal clock is used. If an external clock is forcibly input, the serial interface 0 operates even when the internal clock is set. When the external clock is used (slave operation), the operation continues even when the "HALT" instruction is executed. To release the halt status by using the interrupt of serial interface 0, the internal clock cannot be used as described above.
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19.13 Configuration of Serial Interface 1 (SIO1)
Figure 19-17 shows the block diagram of serial interface 1. As shown in this figure, the shift clock control block of the serial interface 1 consists of a clock I/O pin block, a clock generation block, a wait control block, and a clock count block. The serial data control block consists of a serial data I/O pin block and a presettable shift register 1. These blocks are controlled by the flags of control registers. Data is written to or read from the presettable shift register 1 via data buffer. 19.14 outlines the functions of the respective blocks. Figure 19-17. Block Diagram of Serial Interface 1
Control Register Address 02H
SSSS IIII OOOO 1111 THCC SIKK Z10
Flag symbol
Shift clock l/O pin block WAIT P0B2/ SCK1
P0B2/SCK1 output control Output latch WRITE Port register READ
Shift clock output
CLKOUT Clock control
SF8 Wait control
SF8 Clock counter
P0BBIO2 flag Serial clock input Serial data l/O pin block
Data Buffer (DBF) Address Symbol Data 0CH DBF3 0DH DBF2 0EH DBF1 M S B 0FH DBF0 L S B
P0B1/ SO1
P0B1/SO1 output control
Output latch
WRITE Port register READ
P0BBIO1 flag P0B0/ SI1
Output latch
03H Serial out data
WRITE Port register READ
DATAOUT
Presettable shift register 1
CLKIN DATAIN
P0BBIO0 flag Serial in data
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19.14 Functional Outline of Serial Interface 1
Serial interface 1 can be used in three-line serial I/O mode as indicated in Table 19-1. This interface uses the P0B2/SCK1, P0B1/SO1, and P0B0/SI1 pins. Serial interface 1 can operate with an internal clock or external clock. Moreover, reception or transmission can be selected. The following 19.14.1 through 19.14.6 outline the functions of the respective blocks of serial interface 1. For the details of the respective blocks, refer to 19.15 through 19.9. 19.14.1 Shift clock I/O pin block This block selects a shift clock I/O pin. The shift clock I/O pin is selected by the serial I/O1 mode register. For details, refer to 19.15. 19.14.2 Serial data I/O pin block This block selects a serial data I/O pin. The serial data I/O pin is selected by the serial I/O1 mode select register. For details, refer to 19.15. 19.14.3 Clock generation block This block selects the clock frequency of the shift clock and controls the shift clock output timing. The clock frequency is selected by the serial I/O1 mode select register. For details, refer to 19.16. 19.14.4 Clock counter This counter counts the rising edges of the clock output by the shift clock output pin and outputs a signal at the eighth clock (SF8 signal). The SF8 signal is used to place serial communication in the wait (pause) status. For details, refer to 19.17. 19.14.5 Presettable shift register 1 (SIO1SFR) This shift register sets serial out data and stores serial in data. It performs a shift operation in response to the clock input to the shift clock I/O pin, and inputs or outputs data. The output data is set and the input data is read via data buffer. For details, refer to 19.18. 19.14.6 Wait control block This block controls the wait (pause) and wait release (communication operation) states of serial communication. The wait status of serial communication is set or released by the serial I/O1 mode select register. For details, refer to 19.19.
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19.15 Shift Clock and Serial Data I/O Pin Control Block
The shift clock and serial data I/O pin control block controls the setting of the respective pins and transmission or reception operation of serial interface 1. These control operations are performed by the serial I/O1 mode select register. 19.15.1 describe the configuration and function of the serial I/O1 mode select register. 19.15.2 shows the status of each pin set by the serial I/O1 mode select register. 19.5.1 Configuration and function of serial I/O1 mode select register (SIO1MODE) The configuration and function of the serial I/O1 mode select register are illustrated below. The SIO1CK1 and SIO1CK0 flags select the internal or external clock, and sets the frequency of the internal clock. For the details of the clock, refer to 19.16. The SIO1TS flag sets or releases the wait status of serial interface 1. For the details of the wait operation, refer to 19.19.
Flag Symbol Name b3 S I Serial l/O1 mode select register (SIO1MODE) O 1 T S b2 S I O 1 H I Z b1 S I O 1 C K 1 b0 S I O 1 C K 0 02H R/W Address
Read/ Write
Sets l/O clock frequency of serial interface 1 0 0 1 1 0 1 0 1 External clock (slave) 37.5 kHz (master) 75 kHz (master) 450 kHz (master)
Sets P0B1/SO1 pin as serial out pin 0 1 General-purpose l/O port Serial out
Starts serial communication of serial interface 1 0 1 Does not perform serial communication (wait) Performs serial communication (releases wait)
On reset
Power-ON Clock stop CE
0 0 0
0 0 0
0 0 0
0 0 0
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19.15.2 Pin status set by serial I/O1 mode select register Table 19-9 shows the pin status set by the serial I/O1 mode select register. As shown in this table, the I/O select flag must be manipulated to set each pin. For the details of the I/O select flag, refer to 15. GENERAL-PURPOSE PORTS. Table 19-9. Pin Status Set by Serial I/O1 Mode Select Register
SIO1MODE Pin
--------------------------------------------------------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------------------------------------------------------
Communication mode
b2
Setting of serial output
b1
b0
--------------------------------------------------------------------------------------------------------------------------------------------------
Clock direction
Pin symbol
I/O select flag of each pin
Set pin status
----------------------------------------------------------------------------------------------------------------------------------------
S I O 1 H I Z 3-line serial I/O
S I O 1 C K 1 0
S I O 1 C K 0 0
P 0 B B I O 2 External clock P0B2/SCK1 0
P 0 B B I O 1
----------------------------------------------------------------------------------------------------------------------------------------
P 0 B B I O 0 In wait status: General-purpose input port On release of wait: External clock input In wait status: General-purpose output port On release of wait: General-purpose output port In wait status: General-purpose input port On release of wait: General-purpose input port In wait status: High-level output On release of wait: Internal clock output General-purpose input port General-purpose output port General-purpose input port Serial output 0 1 Serial input General-purpose output port
1
0
1
Internal clock
0
-----------1 0
-----------1 1
1
0 General-purpose output port 1 Serial output
P0B1/SO1
0 1 0 1
P0B0/SI1
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19.16 Clock Generation Block
The clock generation block generates a clock when the internal clock is used (master operation) and controls the clock output timing. The internal clock frequency fSC is set by the SIO1CK1 and SIO1CK0 flags of the serial I/O1 mode select register. The shift clock is successively output, until the current value of the clock counter described in 19.17 reaches "8". 19.6.1 below describes the clock output waveform and generation timing. 19.16.1 Internal shift clock generation timing (1) When wait status is released from initial status The "initial status" is the point at which the internal clock is selected, and the P0B2/SCK1 pin is set in the output mode to output a high level. In the wait status, a high level is output to the P0B2/SCK1 pin.
H 450 kHz L 1/2fSC 1/fSC Serial communication in progress H 75 kHz L 1/3fSC 1/fSC H 37.5 kHz L 1/2fSC 1/fSC Wait status 1/2fSC 2/3fSC Wait status 1/2fSC
Initialization
Wait released
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(2) When wait operation is performed For the details of the wait operation, refer to 19.19. (a) When wait status is set because value of clock counter has reached "8" (normal operation)
H Shift clock pin L Wait released status Wait period Wait Wait released 1/fSC
(b) When forced wait status is set during wait status
H Shift clock pin L Wait period Forced wait by SIO1TS Wait period
(c) When forced wait status is set during wait release At this time, the clock counter is reset.
H Shift clock pin L Wait released status Wait period Wait released 1/fSC
Forced wait by SIO1TS H Shift clock pin L Wait released status Forced wait by SIO1TS
Wait period Wait released
1/fSC
(d) If wait status is released during wait release In this case, the clock output waveform is not changed. The clock counter is not reset, either. (e) If clock frequency is changed and wait status is released at the same time The clock frequency can be changed and the wait status can be released by using the serial I/O1 mode select register of the control registers. Therefore, the clock frequency can be changed and the wait status can be released by one instruction. When this is done, the operation is the same as releasing the wait status from the initial status as described in (1) above.
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19.17 Clock Counter
The clock counter is a wrap-around counter that counts the number of clocks input to or output from the shift clock pin (P0B2/SCK1 pin). The clock counter directly reads the status of the shift clock pin. At this time, whether the clock is the internal clock or external clock is not judged. The clock counter does not operate in the wait status of serial communication. Serial communication is placed in the wait status at the rising edge of the shift clock when the current value of the clock counter is "8". The contents of the clock counter can not be read directly by the program. The following 19.17.1 and 19.17.2 describe the operation and reset condition of the clock counter. 19.7.1 Operation of clock counter Figure 19-18 shows the operation of the clock counter. The initial value of the clock counter is "0". The clock counter is incremented each time the falling edge of the shift clock pin has been detected. After its value has been incremented to "8", it is reset to "0" at the next rising edge of the shift clock pin. When the clock counter has been reset to 0, serial communication is placed in the wait status. Figure 19-18. Operation of Clock Counter
H Shift clock pin L H Serial data pin L D7 D6 D5 D1 D0 1 2 3 7 8
Clock counter
0
1
2
3
7
8
0
Wait released Clock counter reset
Wait
19.17.2 Reset (0) condition of clock counter The clock counter is reset to 0 under the conditions (1) through (5) below. (1) On power-ON reset (2) On execution of clock stop instruction (3) When "0" has been written to the SIO1TS flag (forced wait) (4) When the wait status is released and the shift clock rises when the current value of the clock counter is "8" (5) On CE reset
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19.18 Presettable Shift Register 1 (SIO1SFR)
The presettable shift register 1 (SIO1SFR) is an 8-bit shift register that writes serial out data and reads serial in data. Data is written to or read from the presettable shift register 1 by the "PUT" or "GET" instruction via data buffer. 19.18.1 describes the configuration of the presettable shift register 1 and its relation with the data buffer. The data of the presettable shift register 1 is shifted in synchronization with the clock applied to the shift clock pin (P0B2/SCK1 pin). At this time, the most significant bit (MSB) of the presettable shift register 1 is output to the serial data output pin (P0B1/SO1 pin) in synchronization with the falling edge of the shift clock, and the data of the serial data input pin (P0B0/ SI1 pin) is read to the least significant bit (LSB) of the presettable shift register 1 in synchronization with the rising edge of the clock. 19.8.2 describes the operation. 19.18.3 describes the points to be noted in writing or read data to or from the presettable shift register 1. The presettable shift register 1 does not shift data in the wait status. For the details of the operations of the register in the respective serial communication modes, refer to 19.20. 19.18.1 Configuration of presettable shift register 1 and its relation with data buffer The configuration of the presettable shift register 1 and its relation with the data buffer are illustrated below.
Name Symbol Address Bit Data b3 Data Buffer DBF3 0CH b2 b1 b0 b3 DBF2 0DH b2 b1 b0 b3 DBF1 0EH b2 b1 b0 b3 DBF0 0FH b2 b1 b0
Don't care
Don't care
Transfer data
8 Peripheral Register Name b7 M S B b6 b5 b4 b3 b2 b1 b0 L S B
GET can be executed PUT can be executed
Peripheral address
Symbol
Peripheral hardware
Presettable shift register 0
SIO1SFR
03H
Serial interface 1
Valid data
Setting of serial out data and reading serial in data D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Serial out Serial in
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19.18.2 Operation of presettable shift register 1 Figure 19-19 shows the data shift operation of the presettable shift register 1. Table 19-10 shows the data shift operation during reception or transmission. Figure 19-19. Data Shift Operation of Presettable Shift Register 1
H Shift clock pin L Wait released Clock counter 0 1 2 6 7 8 0 1 2 3 6 7 8
H Serial data input pin L H Serial data output pin L D7 D6 D5 D2 D1 D0 d7 d6 d5 d2 d1 d0
b7 b6 b5 b4 b3 b2 b1 b0
D7 D6 D5 D4 D3 D2 D1 D0
D6 D5 D4 D3 D2 D1 D0 d7
D5 D4 D3 D2 D1 D0 d7 d6
D1 D0 d7 d6 d5 d4 d3 d2
D0 d7 d6 d5 d4 d3 d2 d1
d7 d6 d5 d4 d3 d2 d1 d0
Presettable shift register 1
Table 19-10. Data Shift Operation during Reception and Transmission Serial I/O Mode Serial input operation Status of P0B0/SI1 pin is shifted from LSB and input at rising edge of shift clock pin. Contents of output latch are input when P0BBIO0 flag is "0". Does not operate in wait status. Serial output operation Data is shifted from MSB and output to P0B1/ SO1 pin at falling edge of shift clock pin. Data is not output if P0BBIO1 flag is "1" or SIO1HIZ flag is "0". Does not operate in wait status.
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19.18.3 Notes on setting and reading data To set data to the presettable shift register 1, use the "PUT SIO1SFR, DBF" instruction. To read data, use the "GET DBF, SIO1SFR" instruction. Set or read data in the wait status. While the wait status is released, data may not be correctly set or read depending on the status of the shift clock pin. Table 19-11 shows the timing of setting and reading data, and points to be noted. Table 19-11. Reading (GET) and Writing (PUT) Data of Presettable Shift Register 1 and Notes Status on Execution of PUT/GET Wait status Read (GET) Write (PUT) External clock Floating Internal clock High level Normal read Normal write Outputs MSB contents as data when wait status is released next time (during transmission) (However, if shift clock is low in wait status when external clock is used, data cannot be correctly written and contents of SIO1SFR are lost.)
Clock Data PUT SIO1SFR, Wait released DBF MSB
Status of Shift Clock Pin
Presettable Shift Register 1 (SIO1SFR)
Wait released status
Read (GET)
Low level High level
Normal read Normal read (When internal clock is selected, set value is shifted 1 bit and is read (MSB is shifted to LSB).)
Write (PUT)
High level
Normal write Outputs MSB contents when shift clock falls. Clock counter is not reset.
Clock Data PUT SIO1SFR, DBF MSB
Low level
Cannot be written normally. Contents of SIO1SFR are lost.
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19.19 Wait Block
The wait block places communication of serial interface 1 in the wait status or releases the wait status. The wait block is controlled by the SIO1TS flag of the serial I/O1 mode select register. 19.19.1 below describes the wait operation and points to be noted. 19.19.1 Wait operation and notes In the wait status, the clock generation block and presettable shift register 1 stop operation, and therefore, serial communication stops. Serial communication can be executed by releasing the wait status. To release the wait status, write "1" to the SIO1TS flag. When "1" is written to the SIO1TS flag, the internal clock is output to the shift clock output pin (when the device is operating as the master), and the presettable shift register 1 and clock counter start operating. If the shift clock rises when the current value of the clock counter is "8", the wait status is set. At this time, the SIO1TS flag is automatically reset to 0. By detecting the contents of the SIO1TS flag when the wait status has been released, the operation status of serial communication can be checked. Therefore, by writing "1" to the SIO1TS flag and then detecting "0" of the SIO1TS flag after serial communication has been started, data is read or set. If data is set to the presettable shift register 1 (by using the PUT instruction) or data is read (by using the GET instruction) while the wait status is released, the correct data may not be set or read. For details, refer to 19.18.3 Notes on setting and reading data. If "0" is written to the SIO1TS flag while the wait status is released, the wait status is set. This is called "forced wait status". If the forced wait status is set, the clock counter is reset to "0". Figure 19-20 shows an example of the wait operation.
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Figure 19-20. Example of Wait Operation
H Shift clock pin L H Serial data input pin L H Serial data output pin L Clock counter 1 SIO1TS 0 Wait status Wait status released Wait status Previous value D7 D6 D5 D1 D0 d7 d6 d5 d1 d0 1 2 3 7 8
0
1
2
3
7
8
0
Wait released
Wait
When the wait status is released, serial data is output at the falling edge of the next clock, and the wait status is set. When eight pulses of the serial clock have been input, the shift clock pin outputs a high level, and the clock counter and presettable shift register 1 stop operating. If data is written to or read from the presettable shift register 1 while the wait status is released and the shift clock pin is high, the correct data is not set. If data is written to the presettable shift register while the wait status is released and the shift clock pin is low, the contents of the MSB are output to the serial data output pin as soon as the "PUT" instruction has been executed. If the forced wait status is set while the wait status is released, the wait status is set immediately when "0" has been written to the SIO1TS flag, and the clock counter is reset to "0".
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19.20 Using Serial Interface 1
Figure 19-21 shows the I/O block and communication method of serial interface 1. Table 19-12 shows the operation in each mode of serial interface 1. As shown in Figure 19-21 and Table 19-12, serial interface 1 can operate on an internal clock (master) or external clock (slave), and can perform reception or transmission. The master or slave operation is selected by the SIO1CK1 and SIO1CK0 flags, and the reception or transmission is selected by the SIO1HIZ flag. During the master operation, the internal shift clock is output from the P0B2/SCK1 pin. However, the P0B2/SCK1 pin must be set in the output port mode (P0BBIO2 flag = 1). During the slave operation, the P0B2/SCK1 pin is floated, and the device waits for the external clock. However, the P0B2/SCK1 pin must be set in the input port mode (P0BBIO2 flag = 0). Serial data is output from the P0B1/SO1 pin at the falling edge of the shift clock, regardless of whether the internal clock or external clock is selected, when serial data is output. However, the P0B1/SO1 pin must be set in the output mode (P0BBIO1 flag = 1), and the SIO1HIZ flag must be set. The status of the P0B0/SI1 pin is input to the presettable shift register 1 at the rising edge of the shift clock, regardless of whether the internal clock or external clock is selected, when serial data is input. However, the P0B0/SI1 pin must be set in the input port mode (P0BBIO0 flag = 0). If the value output to the P0B2/SCK1 pin is read, the "status of the output latch at that time" is read in the wait status, and the "status of the pin at that time" is read when the wait status is released. When the value output to the P0B1/SO1 pin is read, the "status of the output latch at that time" is read. Paragraphs (1) through (4) below Table 19-12 show program examples for transmission and reception during master and slave operations.
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Figure 19-21. I/O Block and Communication Method of Serial Interface 1 (1/2) I/O block
P0B2/SCK1 l/O control block P0BBIO2 SIO1TS SIO1CK1 SIO1CK0
Wait signal
VDD
VDD 1 P-ch P0B2/SCK1 N-ch 1 0 0
P0B2 output latch
Shift clock output WRITE Port register READ Shift clock input
P0B1/SO1 l/O control block P0BBIO1 VDD VDD 1 P-ch P0B1/SO1 N-ch 1 0 0
P0B1 output latch
SIO1HIZ
Serial data output WRITE Port register READ
P0B0/SI1 l/O control block P0BBIO0
VDD
VDD P-ch P0B0/SI1 N-ch 1 0
P0B0 output latch
WRITE Port register READ Serial data input
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Figure 19-21. I/O Block and Communication Method of Serial Interface 1 (2/2) Communication method
H SI1 pin L H SO1 pin L H SCK1 pin L Data read Data output Hardware control Wait released Wait status 1 2 3 7 8 D7 D6 D1 D0 d7 d6 d1 d0
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Table 19-12. Operation of Serial Interface 1 in Each Mode
Operation Mode Item Setting status of each pin Slave operation SIO1CK1=SIO1CK0=0 P0B2/SCK1 In wait status When P0BBIO2 = 0 Floating General-purpose input port When P0BBIO2 = 1 General-purpose output port Outputs contents of output latch. Normally, P0BBIO2 is reset to 0. When SIO1HIZ = 0 When P0BBIO1 = 0 General-purpose input port Floating When P0BBIO1 = 1 General-purpose output port Outputs contents of output latch. When wait released When P0BBIO2 = 0 Floating External clock input When P0BBIO2 = 1 General-purpose output port Outputs contents of output latch. 3-line Serial I/O Mode Master operation Other than SIO1CK1=SIO1CK0=0 In wait status When P0BBIO2 = 0 Floating General-purpose input port When P0BBIO2 = 1 Outputs high level. Normally, P0BBIO2 is set to 1. When wait released When P0BBIO2 = 0 Floating General-purpose input port When P0BBIO2 = 1 Outputs internal clock
P0B1/SO1
When SIO1HIZ = 1 When P0BBIO1 = 0 General-purpose input port Floating When P0BBIO1 = 1 Outputs serial data.
When SIO1HIZ = 0 When P0BBIO1 = 0 General-purpose input port Floating When P0BBIO1 = 1
General-purpose output port Outputs contents of output latch.
When SIO1HIZ = 1 When P0BBIO1 = 0 General-purpose input port Floating When P0BBIO1 = 1 Outputs serial data.
P0B0/SI1
Clock counter operation Operation of presettable shift register 1 (SIO1SFR)
Wait operation
When P0BBIO0 = 0 Floating Waits for input of external data When P0BBIO0 = 1 General-purpose output port Outputs contents of output latch. Normally, P0BBIO0 is reset to 0. Incremented at falling edge of SCK1 pin Output When SIO1HIZ = 1 Shifts data from MSB at falling edge of SCK1 pin and outputs it from SO1 pin. When SIO1HIZ = 0 Does not output data. Input Shifts data of SI1 pin from LSB and inputs it at rising edge of SCK1 pin regardless of P0BBIO0. However, contents of output latch are output to SI1 pin when P0BBIO0 = 1. Serial communication is started when "1" is written to SIO1TS. SIO1TS is reset to "0" at rising edge of shift clock when clock counter value is "8". Refer to above for operation of each pin.
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(1) Program example of serial interface 1 (master transmission mode) Example To transmit 2-byte data "A596H" SCK1BIO FLG SO1BIO FLG MOV MOV PUT SET2 DBF1, #0AH DBF0, #5 SIO1SFR, DBF SCK1BIO, SO1BIO ; Releases wait, serial output ; Master (fSC = 37.5 kHz) LOOP1: SKF1 BR MOV MOV PUT SET1 LOOP2: SKF1 BR ... (2) Program example of serial interface 1 (master reception mode) Example To receive and store 2-byte data to addresses 00H through 03H of BANK0 SCK1BIO FLG SI1BIO FLG P0BBIO2 P0BBIO0 0.00H 0.01H 0.02H 0.03H ; Stores higher 4 bits of first byte ; Stores lower 4 bits of first byte ; Stores higher 4 bits of second byte ; Stores lower 4 bits of second byte DATA1H MEM DATA1L MEM DATA2H MEM DATA2L MEM INITFLG SCK1BIO, NOT SI1BIO INITFLG SIO1TS, NOT SIO1HIZ, SIO1CK1, SIO1CK0 ; Releases wait, no serial output ; Master (fSC = 450 kHz) SIO1TS LOOP2 ; Waits until wait status is released SIO1TS LOOP1 DBF1, #9 DBF0, #6 SIO1SFR, DBF SIO1TS ; Releases wait ; Sets transmit data ; Waits until wait status is released P0BBIO2 P0BBIO1 ; Sets transmit data
INITFLG SIO1TS, SIO1HIZ, NOT SIO1CK1, SIO1CK0
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LOOP1: SKF1 BR GET ST ST SET1 LOOP2: SKF1 BR GET ST ST ... (3) Program example of serial interface 1 (slave transmission mode) Example To transmit 2-byte data "A596H" SCK1BIO FLG SO1BIO FLG P0BBIO2 P0BBIO1 INITFLG NOT SCK1BIO, SO1BIO MOV MOV PUT DBF1, #0AH DBF0, #5 SIO1SFR, DBF ; Releases wait, serial output, slave LOOP1: SKF1 BR MOV MOV PUT SET1 LOOP2 SKF1 BR ... SIO1TS LOOP2 ; Waits until wait status is released SIO1TS LOOP1 DBF1, #9 DBF0, #6 SIO1SFR, DBF SIO1TS ; Releases wait ; Sets transmit data ; Waits until wait status is released ; Sets transmit data INITFLG SIO1TS, SIO1HIZ, NOT SIO1CK1, NOT SIO1CK0 SIO1TS LOOP2 DBF, SIO1SFR DATA2H, DBF1 DATA2L, DBF0 ; Reads receive data ; Stores read data ; Wait until wait status is released SIO1TS LOOP1 DBF, SIO1SFR DATA1H, DBF1 DATA1L, DBF0 SIO1TS ; Releases wait ; Reads receive data ; Stores read data ; Waits until wait status is released
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(4) Program example of serial interface 1 (slave reception mode) Example To receive and store 2-byte data to addresses 00H through 03H of BANK0 SCK1BIO FLG SI1BIO FLG P0BBIO2 P0BBIO0 0.00H 0.01H 0.02H 0.03H ; Stores higher 4 bits of first byte ; Stores lower 4 bits of first byte ; Stores higher 4 bits of second byte ; Stores lower 4 bits of second byte
DATA1H MEM DATA1L MEM DATA2H MEM DATA2L MEM CLR2
SCK1BIO, SI1BIO ; Releases wait, no serial output, slave
INITFLG SIO1TS, NOT SIO1HIZ, NOT SIO1CK1, NOT SIO1CK0 LOOP1: SKF1 BR GET ST ST SET1 LOOP2 SKF1 BR GET ST ST ... SIO1TS LOOP2 DBF, SIO1SFR DATA2H, DBF1 DATA2L, DBF0 ; Reads receive data ; Stores read data ; Waits until wait status is released SIO1TS LOOP1 DBF, SIO1SFR DATA1H, DBF1 DATA1L, DBF0 SIO2TS ; Releases wait ; Reads receive data ; Stores read data ; Waits until wait status is released
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19.21 Reset Status of Serial Interface 1
19.21.1 At power-ON reset All the P0B2/SCK1 through P0B0/SI1 pins are set in the general-purpose input port mode (floating output). The value of the presettable shift register 1 is undefined. 19.21.2 On execution of clock stop instruction All the P0B2/SCK1 through P0B0/SI1 pins are set in the general-purpose input port mode (floating output). The presettable shift register 1 retains the previous value. 19.21.3 At CE reset All the P0B2/SCK1 through P0B0/SI1 pins are set in the general-purpose input port mode (floating output). The presettable shift register 1 retains the previous value. 19.21.4 In halt status The I/O pins retain the current status. If the internal clock is used (master operation) at this time, the clock is not output when the "HALT" instruction has been executed. Therefore, the "HALT" instruction must be executed after communication has been completed when the internal clock is used. If an external clock is forcibly input, the serial interface 1 operates even when the internal clock is set. When the external clock is used (slave operation), the operation continues even when the "HALT" instruction is executed.
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20. FREQUENCY COUNTER (FC)
The frequency counter (FC) is used to measure the intermediate frequency (IF) of a tuner or to detect the pulse width of an external signal.
20.1 Configuration of Frequency Counter
Figure 20-1 shows the block diagram of the frequency counter. As shown in this figure, the frequency counter consists of an FCG I/O select block, an IF counter input select block, a gate time control block, a start/stop control block, and a count block. Figure 20-1. Block Diagram of Frequency Counter
Control register
Data buffer
P1A0/FCG P1D3/FMIFC P1D2/AMIFC
FCG l/O select block IF counter input select block Gate time control block Start/stop control IF counter (16 bits)
Interrupt control
20.2 Functional Outline of IF Counter
The frequency counter has an IF count function to count the frequency of an externally input signal and an external gate counter (FCG: Frequency for external Gate signal) to detect the pulse width of an externally input signal. The IF counter function counts the frequency input to the P1D3/FMIFC or P1D2/AMIFC pin for a fixed time (1 ms, 4 ms, 8 ms, or open) with a 16-bit counter. The external gate counter (FCG) function counts the frequency of the internal clock (1 kHz, 100 kHz, or 900 kHz) from a rising edge of the signal applied to the P1A0/FCG pin to the next rising edge by using a 16-bit counter. For the details of the IF counter and external gate functions, refer to 20.5 and 20.6, respectively. Because the frequency counter shares the hardware with the clock generator port described in 18. CLOCK GENERATOR PORT (CGP), the frequency counter and clock generator port cannot be used at the same time. For details, refer to 20.8 Notes on Using Frequency Counter. 20.2.1 IF counter input select block and FCG I/O select block The IF counter input select block selects whether the P1D3/FMIFC and P1D2/AMIFC pin is used as general-purpose input port pins or IF counter pins. The FCG I/O select block selects whether the P1A0/FCG pin is used as a general-purpose I/O port pin or external gate counter pin. Selection of the general-purpose port function, IF counter function, or external gate function is made by using the IF counter mode select register (IFCMODE: RF address 12H). For details, refer to 20.3.
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20.2.2 Gate time control block The gate time control block controls the time during which the frequency is counted, by using the IF counter mode select register. The following paragraphs (1) and (2) outline the operations of the IF counter function an external gate counter function. For details, refer to 20.3. (1) IF counter function This function is to set the internal gate time (1 ms, 4 ms, 8 ms, or open) to count the frequency applied to the P1D3/FMIFC or P1D2/AMIFC pin, by using the IF counter mode select register. (2) External gate counter function This function is to count the internal frequency (1 kHz, 100 kHz, or 900 kHz) during the external gate time (the time from a rising edge of the signal applied to the P1A0/FCG pin to the next rising edge), by using the IF counter mode select register. 20.2.3 Start/stop control block The start/stop control block starts or stops the frequency counter by using the IF counter control register (IFCCONT: RF address 23H), IF counter gate open status register (IFCGOSTR: RF address 04H), and IF counter interrupt request register (IREQIFC: RF address 3AH). When the IF counter function is used, the start/stop control block issues an interrupt request when the internal gate is closed. For details, refer to 20.4. 20.2.4 IF counter The IF counter counts the input frequency when the IF counter function or external gate counter function is used, by using a 16-bit binary counter. The count value is read by the IF counter data register (IFC: peripheral address 43H) via data buffer. For details, refer to 20.4.
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20.3 I/O Select Block and Gate Time Control Block
20.3.1 Configuration of I/O select block and gate time control block Figure 20-2 shows the configuration of the IF counter input select, external gate counter I/O select, and gate time control blocks. Figure 20-2. Configuration of I/O Select Block and Gate Time Control Block
Control Register 35H b3 b2 b1 b0 b3 P 1 A B I O 3 P 1 A B I O 2 P 1 A B I O 1 P 1 A B I O 0 I F C M D 1
Address Bit
12H b2 b1 I F C M D 0 I F C C K 1
b0 I F C C K 0
Flag symbol
2-4 decoder
CGP
VDD F C G P1A0/FCG FMIFC AMIFC FCG Gate signal
l/O port
F M I F C
Gate signal generator (1, 4, 8 ms) Frequency generator (9,100,900 kHz)
VDD FCG P1D3/FMIFC 1/2 FMIFC AMIFC A M I F C Frequency
Input port
VDD
P1D2/AMIFC
Input port
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20.3.2 Function of I/O select block The I/O select block selects whether each pin is used as a general-purpose I/O port pin or frequency counter pin. The selection is made by using the IFCMD1 and IFCMD0 flags of the IF counter mode select register (refer to 20.3.4). To use the P1A0/FCG pin as an external gate counter pin, the P1ABIO0 flag of the port 1A bit I/O register must be reset to "0". This is because the P1A0/FCG pin functions as a general-purpose output port pin if the P1ABIO0 flag is set to "1", even when the external gate counter function is selected by the IFCMD1 and IFCMD0 flags. 20.3.3 Function of gate time control block The gate time control block sets the gate time (count time) when the IF counter function is used and the count frequency when the external gate counter function is used. The gate time and count frequency are set by the IFCCK1 and IFCCK0 flags of the IF counter mode select register (refer to 20.3.4).
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20.3.4 Configuration and function of IF counter mode select register (IFCMODE) The IF counter mode select register selects the IF counter function or external gate counter function. The configuration and function of this register are illustrated below. Because the frequency counter is multiplexed with the clock generator port, this register can also select the clock generator port function.
Flag Symbol Name b3 I F IF counter mode select register (IFCMODE) C M D 1 b2 I F C M D 0 b1 I F C C K 1 b0 I F C C K 0 12H R/W Address Read/ Write
Sets gate time of IF counter and reference frequency of external gate counter Gate time of IF counter 0 0 1 1 0 1 0 1 1 ms 4 ms 8 ms Open
Reference frequency of external gate counter
1 kHz 100 kHz 900 kHz 0 kHz
Selects functions of IF counter, external gate counter (FCG), or clock generator port (CGP) 0 0 1 1 0 1 0 1 Clock generator port (CGP) IF counter (FMIFC) IF counter (AMIFC) External gate counter (FCG)
On reset
Power-ON Clock stop CE
0 0
0 0
0 0
0 0
Retained
The IF counter, external gate counter, and clock generator port functions cannot be used at the same time.
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20.4 Start/Stop Control Block and IF Counter
20.4.1 Configuration of start/stop control block and counter Figure 20-3 shows the configuration of the start/stop control block and counter. Figure 20-3. Configuration of Start/Stop Control Block and Counter
Control Register Address 3AH Control Register Address 04H Control Register Address 23H
Bit
Flag symbol
b3 b2 b1 b0 I R Q I 000F C
Bit
Flag symbol
b3 b2 b1 b0 I F C G 000O S T T
Bit
Flag symbol
b3 b2 b1 b0 I I FF CC SR 00TE RS T
Data Buffer (DBF) Address 0CH 0DH 0EH Symbol DBF3 DBF2 DBF1 M S Data B
0FH DBF0 L S B
16 Turned OFF by FCG Interrupt block 16 From l/O select block Gate signal Frequency Start/stop RES
Peripheral address 43H
IF counter data register (lFC)
IF counter (16 bits) Higher 6 bits are multiplexed with CGP counter
6 CGP counter
20.4.2 Function of start/stop control block The start/stop control block starts or stops counting of the frequency counter. The counter is started by the IFCSTRT flag of the IF counter control register. It is stopped by the IFCGOSTT flag of the IF counter gate open status register or the IRQIFC flag of the IF counter interrupt request register. Note, however, that the stop of the counter cannot be detected by the IFCGOSTT flag when the the external gate counter function is used. The following 20.4.3 and 20.4.4 describe the operations when the IF counter function and external gate function are selected. 20.4.7 and 20.4.8 describe the configuration and function of the IF counter control register and IF counter gate open status register.
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20.4.3 Gate operation of IF counter function (1) When 1, 4, or 8 ms of gate time is selected The gate is opened for 1, 4, or 8 ms starting from the rising edge of the internal 1-kHz signal after the IFCSTRT flag has been set to 1, as illustrated below. While this gate is open, the frequency input from the specified pin is counted by the 16-bit counter. When the gate is closed, the IFCGOSTT flag is reset, and IRQIFC flag is set. The IFCGOSTT flag is automatically set to 1 when the IFCSTRT flag is set. The IRQIFC flag is reset when an interrupt has been accepted or when "0" has been written to it.
H L OPEN CLOSE
Internal 1 kHz 1 ms
Gate time
4 ms 8 ms Count period (lFCGOSTT flag = 1) Actual gate is opened during at this point. IFCSTRT flag is set. IFCGOSTT flag is set at this point. Count ends IFCGOSTT flag is reset and IRQIFC flag is set.
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(2) When "open" is selected as gate time When "open" is selected as the gate time by the IFCCK1 and IFCCK0 flags, the gate is opened as illustrated below. If the counter is started by the IFCSTRT flag while the gate is open, the gate is closed after undefined time. Therefore, do not set the IFCSTRT flag to 1 when the gate is opened. However, the counter can be reset by the IFCRES flag.
H L OPEN CLOSE
Internal 1 kHz Gate
Count period If the IFCSTRT flag is set during this period, the gate is closed after undefined time. Set IFCCK1 = IFCCK0 = 1. The gate is aetually opened at this time. If the gate is opened when the IFCGOSTT flag is 1, the gate is closed after undefined time.
If "open" is selected as the gate time, the gate is opened or closed in two ways as illustrated in (a) and (b) below. (a) Gate time is set to other than open by IFCCK1 and IFCCK0 flags
Gate OPEN CLOSE
Count period Set IFCCK1 = IFCCK0 = 1 Other than open is selected by IFFCCK1 and IFCCK0
(b) Pin selected by IFCMD1 and IFCMD0 flags is unselected The gate remains open, and counting is stopped by disabling input from the pin.
Gate OPEN CLOSE
Count time Set IFCCK1 = IFCCK0 = 1 Sets IFCMD1 = IFCMD0 = 0 (CGP) FMIFC and AMIFC pins are unselected and count input is not made.
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20.4.4 Gate operation of external gate counter (FCG) The gate is opened starting from the rising edge of the signal input to the pin to the next rising edge after the IFCSTRT flag has been set, as shown below. While the gate is open, the internal frequency (1 kHz, 100 kHz, or 900 kHz) is counted by the 16-bit counter. When the gate is closed, the IRQIFC flag is set. The IRQIFC flag is reset when an interrupt is accepted or when "0" is written to it. Even if the IFCSTRT flag is set, the IRQIFC flag is not automatically reset. This flag therefore must be reset by program when the counter is started. The IFCGOSTT flag is automatically set to 1 when the IFCSTRT flag is set, but is not reset when the gate is closed. In other words, opening or closing of the gate cannot be detected by the IFCGOSTT flag when the external gate counter function is used.
H L OPEN CLOSE
External signal Gate time
Count period Gate is opened at this point. IFCSTRT flag 1 Count ends IRQIFC flag is set. IFCGOSTT flag is "undefined".
When counter is reset and started while gate is open
External signal Gate time
H L OPEN CLOSE
Count period
Count period Gate is opened at this point. Count ends IRQIFC flag is set. IFCGOSTT flag is "undefined".
IFCSTRT flag 1
IFCSTRT flag 1Note
Note
If the IFCRES flag is set at this point, the IRQIFC flag is reset to "0".
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20.4.5 Function and operation of 16-bit counter The 16-bit counter counts up the frequency input during gate time. This counter is reset by writing "1" to the IFCRES flag of the IF counter control register. When the 16-bit counter counts up to FFFFH, it is reset to 0000H and continues counting. Because the higher 6 bits of this counter are multiplexed with the clock generator port function, the frequency counter and clock generator port cannot be used at the same time. The following paragraphs (1) and (2) describe the operations of the IF counter function and external gate counter function. The value of the IF counter data register is read via data buffer. 20.4.6 describes the configuration and function of the IF counter data register. (1) When IF counter function is used The 16-bit counter counts the frequency input to the P1D3/FMIFC or P1D2/AMIFC pin while the gate is open. Note, however, that the frequency input to the P1D3/FMIFC pin is divided by two. The relation between count value "x (HEX)" and input frequencies (fFMIFC and fAMIFC) is shown below. FMIFC fFMIFC = AMIFC fAMIFC = x(DEC) tGATE (2) When external gate function is used The 16-bit counter counts the internal frequency while the gate is opened by the signal input to the P1A0/ FCG pin. The relation between count value "x (HEX)" and gate width tGATE of the input signal is shown below. x(DEC) fr (kHz) tGATE: gate time (1 ms, 4 ms, 8 ms) x(DEC) tGATE x 2 (kHz) tGATE: gate time (1 ms, 4 ms, 8 ms)
tGATE =
(ms)
fr:
internal frequency (1 kHz, 100 kHz, 900 kHz)
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20.4.6 Configuration and function of IF counter data register (IFC) The configuration and function of the IF counter data register are illustrated below. The IF counter data register reads the count value of the frequency counter. The IF counter data register counts up to FFFFH, then is reset to 0000H on the next input and continues counting.
Name Symbol Address Bit Data DBF3 0CH Data Buffer DBF2 0DH DBF1 0EH DBF0 0FH
b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 Transfer data GET can be executed Nothing is changed by PUT Peripheral Register
16
Name IF counter data register
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Valid data
Symbol IFC
Peripheral address
Peripheral hardware Frequency counter
43H
Count value of frequency counter 0 IF counter function * FMIF counter Counts rising edge of signal applied to P1D3/FMIFC pin via 1/2 divider * AMIF counter Counts rising edge of signal applied to P1D2/AMIFC pin
x
External gate counter function Counts rising edge of internal reference frequency from rising edge of signal applied to P1A0/FCG pin to next rising edge
2 - 1 (FFFFH)
16
The higher 6 bits of the IF counter are multiplexed with the CGP counter. Therefore, the frequency counter function and clock generator port function cannot be used at the same time. For details, refer to 20.8 Notes on Using Frequency Counter.
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20.4.7 Configuration and function of IF counter control register (IFCCONT) The IF counter control register starts the frequency counter function (IF counter and external gate counter) and resets the 16-bit counter.
Flag Symbol Name b3 b2 b1 I F IF counter control register (lFCCONT) C 0 0 S T R T b0 I F C R E S 23H R/W Address Read/ Write
Controls IF counter and count value of external gate counter 0 1 Nothing is changed Resets counter
Sets start of IF counter and external gate counter 0 1 Nothing is changed Starts counting
Fixed to "0"
On reset
Power-ON Clock stop CE
0
0
0 0
0 0
Retained
The IF counter is controlled by writing the contents of the window register to it by using the "POKE" instruction. When the contents of this register are read to the window register by the "PEEK" instruction, "0" is read.
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20.4.8 Configuration and function of IF counter gate open status register (IFCGOSTR) This register detects the opening and closing of the gate when the IF counter function is used. The closing of the gate cannot be detected when the external gate counter function is used. The configuration and function of this register are illustrated below.
Flag Symbol Name b3 b2 b1 b0 I F IF counter gate open status register (IFCGOSTR) C 0 0 0 G O S T T 04H R Address Read/ Write
Detects opening/closing of gate of reference counter When IF counter function is used 0 1 Set to 1 since "1" is set to the IFCSTRT flag until gate time is out
When external gate counter function is used
Reset to 0 after fixed time (gate time of IF counter function) regardless of input to P1A0/FCG pin
Fixed to "0"
On reset
Power-ON Clock stop CE
0
0
0
0 - -
When the IFCGOSTT flag is set to 1 (when the gate is open), do not read the contents of the IF counter data register (IFC) to the data buffer. The gate of the IF external gate counter function cannot be opened or closed by the IFCGOSTT flag. Open or close the gate of the external gate counter by using the IRQIFC flag.
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20.5 Using IF Counter Function
The following subsections 20.5.1 through 20.5.3 describe how to use the hardware of the IF counter, program example, and count error. 20.5.1 Using hardware of IF counter Figure 20-4 shows the block diagram when the P1D3/FMIFC and P1D2/AMIFC pins are used. Table 20-1 shows the range of the frequencies that can be input to the P1D3/FMIFC and P1D2/AMIFC pins. As shown in figure 20-4, the IF counter has an input pin provided with an AC amplifier. Cut off the DC component of the input signal by using capacitor C. When the P1D3/FMIFC and P1D2/AMIFC pins are used for the IF counter function, switch SW turns ON, and the voltage on each pin drops to about 1/2 VDD. If the voltage has not risen to the sufficient intermediate level at this time, the AC amplifier does not operate correctly, and IF counting cannot correctly be performed. Therefore, make sure that a sufficient wait time elapses after each pin has been specified to be used for the IF counter until the counter is started. Figure 20-4. IF Count Function of Each Pin
R SW
C External frequency FMIFC AMIFC To internal counter
Table 20-1. IF Counter Input Frequency Range Input Pin Input Frequency Input Amplitude (MHz) P1D3/FMIFC 5-15 10.5-10.9 P1D2/AMIFC 0.1-1 0.44-0.46 (VP-P) 0.3 0.06 0.3 0.05
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20.5.2 Program example of IF counter function This subsection presents a program example of the IF counter function. As shown in the example below, a wait time must elapse since an instruction that specifies the P1D3/FMICF or P1D2/AMIFC pin as the IF counter pin until the counter is started. This is because the internal AC amplifier does not operate normally as soon as the pin has been selected for the IF counter function, as described in 20.5.1. Example To count frequency of P1D3/FMIFC pin (gate time: 8 ms) INITFLG NOT IFCMD1, IFCMD0, IFCCK1, NOT IFCCK0 ; Selects FMIFC pin and sets gate time to 8 ms Wait SET2 IFCRES, IFCSTRT LOOP SKT1 BR IFCGOSTT READ Processing A BR READ: GET DBF, IFC ; Reads value of IF counter data to data buffer. LOOP ; Detects opening/closing of gate ; Branches to READ: if gate is closed ; Do not read data of IF counter during this processing A ; Do not select CGP function ; Internal AC amplifier stabilization time ; Resets and starts counter
20.5.3 Error of IF counter Errors of the IF counter include an error of the gate time and a count error. Each error is described in (1) and (2) below. (1) Error of gate time The gate time of the IF counter is created by dividing the system clock frequency of 4.5 MHz. If 4.5 MHz shifts by "+x" ppm, therefore, the gate time shifts by "-x" ppm. (2) Count error The IF counter counts the frequency at the rising edge of the input signal. If a high level is input to the pin when the gate is open, one excess pulse is counted. When the gate is closed, however, this excess pulse is not counted depending on the status of the pin. The counter error, therefore, is "+1, -0".
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20.6 Using External Gate Counter Function
The following 20.6.1 through 20.6.3 describe how to use the hardware of the external gate counter, program example, and count error. 20.6.1 Using external gate counter A program example of the external gate counter function is shown below. The external gate counter function is to open or close the gate by using the IRQIFC flag. An interrupt can be generated by the IRQIFC flag. To not use the interrupt, the contents of the IRQIFC flag can be detected by program. Example To set internal frequency to 100 kHz (with interrupt used) INTIFC DAT BR ORG INTIFC GET EI RETI MAIN: INITFLG IFCMD1, IFCMD0, NOT IFCCK1, IFCCK0 ; Selects FCG function and sets internal frequency to 100 kHz IFC_RES_AND_START CLR1 SET EI 20.6.2 Error of external gate counter Errors of the the external gate counter include an error of the internal frequency and a count error. Each error is described in (1) and (2) below. (1) Error of internal frequency The internal frequency of the external gate counter is created by dividing the system clock frequency of 4.5 MHz. If 4.5 MHz shifts by "+x" ppm, therefore, the internal frequency shifts by "-x" ppm. (2) Count error The external gate counter counts frequency at the falling edge of the internal frequency. Therefore, if the internal frequency is low when the gate is open (when the input of the pin rises), one excess pulse is counted. However, when the gate is closed (when the next input of the pin rises), the frequency is not counted due to the count level of the internal frequency. Therefore, the count error is "+1, -0". IRQIFC IPIFC ; Enables interrupt by IRQIFC flag ; Resets and starts counter DBF, IFC ; Reads value of IF counter data register to data buffer 0001H MAIN ; Symbol definition of IF counter interrupt vector address
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20.7 Reset Status
20.7.1 On power-ON reset The P1D3/FMICF and P1D2/AMIFC pins are set as general-purpose input port pins. The P1A0/FCG pin is set as a general-purpose I/O port pin. 20.7.2 On execution of clock stop instruction The P1D3/FMICF and P1D2/AMIFC pins are set as general-purpose input port pins. The P1A0/FCG pin is set as a general-purpose I/O port pin. 20.7.3 On CE reset The P1D3/FMIFC, P1D2/AMIFC, and P1A0/FCG pins retain the previous status. 20.7.4 In halt status The P1D3/FMIFC, P1D2/AMIFC, and P1A0/FCG pins retain the status immediately before the halt status. When releasing the halt status by using the interrupt of the frequency counter at this time, the following point must be noted. Caution If the "HALT" instruction is executed after counting has been started by the IFCSTRT flag and before the gate is actually opened, the gate is not opened. When using the IF counter function, therefore, wait for at least 1 ms before executing the "HALT" instruction. When the external gate counter function is used, execute the "HALT" instruction after the P1A0/FCG pin has gone high. Figure 20-5 illustrates the gate operation when the "HALT" instruction is used. As shown in this figure, closing of the gate cannot be detected if the gate is not opened. Consequently, the interrupt request is not issued. If halt release conditions other than the interrupt are not set and if the interrupts other than that of the IF counter are not enabled, the HALT status is not released. Figure 20-5. Gate Operation When "HALT" Instruction Is Used
OPEN Gate CLOSE
Gate is actually opened at this point. Gate is not opened and interrupt request is not issued if HALT instruction is executed during this period. Sets IFCSTRT flag
356
PD17010
20.8 Notes on Using Frequency Counter
The frequency counter shares the hardware with the clock generator port described in the preceding chapter. Therefore, the clock generator port and frequency counter cannot be used at the same time. If the data of the IF counter mode select register and IF counter data register are manipulated when the clock generator port is used, the operation described in 20.8.1 is performed. If the data of the IF counter mode select register and CGP data register (peripheral address 20H) is manipulated when the frequency counter is used, the operation described in 20.8.2 is performed. 20.8.1 When clock generator port is used (1) When IFCMD1 and IFCMD0 flags of IF counter mode select register are manipulated If a value other than "0" is written to the IFCMD1 and IFCMD0 flags, the P1B0/CGP pin retains the output level at that time when data is set, and stops the CGP operation. If the IFCMD1 and IFCMD0 flags are reset to "0" again, the CGP operation is started. (2) When IF counter data register is manipulated The CGP operation is not affected even if the IF counter data register is read (GET) or written (PUT). An "undefined" value is read when the register is read, and nothing is changed when the register is written. Because the IF counter data register is a read-only peripheral register, do not write data to this register. If the write instruction "PUT IFC, DBF" is executed, the 17K series assembler (AS17K) generates an error. 20.8.2 When frequency counter is used (1) When IFCMD1 and IFCMD0 flags of IF counter mode select register are manipulated If "0" is written to the IFCMD1 and IFCMD0 flags, the P1B0/CGP performs the operation of the CGP data register at that time when the data has been set. To perform the CGP operation, however, the CGPSEL flag of the PWM mode select register must be set. If the previous values are set again to the IFCMD1 and IFCMD0 flags, the frequency counter continues operating, but the count value is not accurate. In other words, the frequency is not counted while the CGP operation is selected. (2) When CGP data register is manipulated The frequency counter is not affected even when the CGP data register is read (GET) or written (PUT). When this register is read, the value set when the CGP function was previously used (if the CGP function was not used, an "undefined value") is read. When the register is written, the contents of the bits 3 through 1 of the DBF1 and DBF0 are written to the CGP data register.
357
PD17010
21. LCD CONTROLLER/DRIVER
The LCD (Liquid Crystal Display) controller/driver can display an LCD of up to 60 dots MAX. by using a combination of segment signals and common signals.
21.1 Configuration of LCD Controller/Driver
Figure 21-1 shows the block diagram of the LCD controller/driver. As shown in this figure, the LCD controller/driver consists of a common signal output timing control block, a segment signal/key source signal output timing control block, a segment signal/output port select block, an LCD segment register, an LCD group register, and a key source signal output control block. 21.2 outlines the function of each block. Figure 21-1. Block Diagram of LCD Controller/Driver
Control register
Data buffer
LCD group register Peripheral register Key source signal output control LCD segment register Data memory space
Common signal output timing control
Segment signal/key source signal output timing control
Segment signal/output port select
CC OO MM 10
L C D 29 / P 0 F 3
L C D 26 / P 0 F 0
L C D 25 / P 0 E 3
L C D 22 / P 0 E 0
L C D 21 / P 0 X 5
L C D 16 / P 0 X 0
L C D 15 / P 0 Y 15 / K S 15
L C D 0 / P 0 Y 0 / K S 0
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PD17010
21.2 Functional Outline of LCD Controller/Driver
The LCD controller/driver can display an LCD of up to 60 dots MAX. by using a combination of common signal output pins (COM1 and COM0 pins) and segment signal output pins (LCD29/P0F3 through LCD0/P0Y0/KS0 pins). Figure 21-2 shows the relation among the common signal output pins, segment signal output pins, and display dots. As shown in this figure, two dots, which are the intersections with the COM1 and COM0 pins, can be displayed per segment line. The drive mode is 1/2 duty, 1/2 bias, and the drive voltage is supply voltage VDD. The segment signal output pins (LCD29/P0F3 through LCD0/P0Y0/KS0) can be also used as general-purpose output port pins. When they are used as general-purpose port pins, port 0F (LCD29/P0F3 through LCD26/P0F0 pins), port 0E (LCD25/ P0E3 through LCD22/P0E0 pins), port 0X (LCD21/P0X5 through LCD16/P0X0 pins), and port 0Y (LCD15/P0Y15/KS15 through LCD0/P0Y0/KS0 pins) can be independently used. Of the segment signal output pins, the LCD15/P0Y15/KS15 through LCD0/P0Y0/KS0 pins can be used as key source signal output pins. The key source signal output pins are multiplexed with the LCD segment output pins by means of time division. For the details of the general-purpose output ports, refer to 15. GENERAL-PURPOSE PORTS. For the details of the key source signal output, refer to 22. KEY SOURCE CONTROLLER/DECODER. The following 21.2.1 through 21.2.6 outline the function of each block of the LCD controller/driver. Figure 21-2. Common Signal Output, Segment Signal Output, and Display Dot
COM1 pin Display dot COM0 pin Segment signal output pin (LCDn)
21.2.1 LCD segment register The LCD segment register sets the dot data on the LCD that is illuminated or extinguished. Because this register is located on the data memory, it can be controlled by any data memory manipulation instruction. When the segment signal output pins are used as general-purpose output port pins, this register sets output data. For details, refer to 21.3. 21.2.2 LCD group register The LCD group register sets the dot data of the LCD that is illuminated or extinguished. Data is set to this register via data buffer. When data is set to the LCD group register, the value of the corresponding LCD segment register changes at the same time. When the segment signal output pins are used as general-purpose output port pins, this register sets the output data. If data is set to the LCD group register at this time, the value of the corresponding LCD segment register is changed at the same time. For details, refer to 21.3.
359
PD17010
21.2.3 Common signal output timing control block The common signal output timing control block controls the common signal output timing of the COM1 and COM0 pins. These pins output low level when LCD display is not performed. Whether LCD display is performed or not is selected by the LCD mode select register (LCDMODE: RF address 10H). For details, refer to 21.4. 21.2.4 Segment signal/key source signal output timing control block The segment signal/key source signal output timing block controls the segment signal output timing of the LCD29/ P0F3 through LCD0/P0Y0/KS0 pins. These pins output low level when LCD display is not performed. Whether LCD display is performed or not is selected by the LCD mode select register. The segment signal/key source signal output timing control block also controls the timing of the segment signals and key source signals output by the LCD15/P0Y15/KS15 through LCD0/P0Y0/KS0 pins. Whether the key source signals are used or not is selected by the LCD mode select register. For details, refer to 21.4. 21.2.5 Segment signal/general-purpose port select block The segment signal/general-purpose port select block selects whether each segment signal output pin is used for LCD display (segment signal output) or as a general-purpose output port pin. This selection is made by using the LCD port select register (LCDPORT: RF address 11H). For details, refer to 21.4. 21.2.6 Key source signal output control block The key source signal output control block sets the key source signal output data output by the LCD15/P0Y15/KS15 through LCD0/P0Y0/KS0 pins and detects the key input timing. The key source signal output data is set by the key source data register (KSR: peripheral address 42H) via the data buffer. The key source data register also sets the output data of port 0Y. To use the key source signal, use the P0D3/ADC5 through P0D0/ADC2 pins as key input pins. For details, refer to 22. KEY SOURCE CONTROLLER/DECODER.
360
PD17010
21.3 LCD Segment Register and LCD Group Register
The LCD segment register and LCD group register sets the display dot on an LCD to be illuminated or extinguished. 21.3.1 Configuration of LCD segment register Figure 21-3 shows the location of the LCD segment register on the data memory. Figure 21-4 shows the configuration of the LCD segment register. Figure 21-3. Location of LCD Segment Register on Data Memory
Column address 0 0 1 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 System register 8 9 A B C D E F BANK0 LCD segment register BANK1 BANK2 BANK3 Data memory 1 2 3 4 5 6 7 8 9 A B C D E F
DBF
Row address
2 3 4 5 6 7
Figure 21-4. Configuration of LCD Segment Register
LCD segment register Address Symbol 60H LCDD0 61H LCDD1 62H LCDD2 63H LCDD3 64H LCDD4 65H LCDD5 66H LCDD6 67H LCDD7 68H LCDD8 69H 6AH 6BH 6CH 6DH 6EH 6FH -
LCDD9 LCDD10 LCDD11 LCDD12 LCDD13 LCDD14
Nothing is allocated. Cannot be used as data memory.
LCDD0 b3 b2 b1 b0
361
PD17010
21.3.2 Function of LCD segment register Figure 21-5 shows the relation between 1 nibble (4 bits) of the LCD segment register and an LCD display dot. As shown in this figure, one nibble of the LCD segment register can set 4 dots of display data (data to be illuminated or extinguished). An LCD display dot corresponding to the LCD segment register bit that is set to "1" lights, and a dot corresponding to the register bit that is reset to "0" remains dark. The LCD segment register sets output data when the segment signal output pin is used as an output port pin. Figure 21-7 shows the relation between the LCD segment register and LCD display dots that are illuminated or extinguished. Figure 21-5. Relation between 1 Nibble of LCD Segment Register and LCD Display Dot
LCD segment register Address Bit m b3 b2 b1 b0
COM1 pin COM0 pin
b3 b2
b1 b0
LCDn-1 pin LCDn pin
362
PD17010
21.3.3 Configuration of LCD group register Figure 21-6 shows the configuration of the LCD group register and its relation with the LCD segment register. Figure 21-6. Configuration of LCD Group Register and Its Relation with LCD Segment Register
Data Buffer (DBF) Address Symbol Data 0CH DBF3 0DH DBF2 0EH DBF1 M S B 0FH DBF0 L S B
Don't care
Don't care
Peripheral address
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
LCD group register
LCDR0 7
LCDR1 4
LCDR2 7 64H 65H
LCDR3 7 66H 67H
LCDR4 7 68H 69H
LCDR5 4 6AH
LCDR6 7 6BH 6CH
LCDR7 7 6DH 6EH 6FH
-
LCD segment register
60H
61H
62H
63H
LCDD0 LCDD1 LCDD2 LCDD3 LCDD4 LCDD5 LCDD6 LCDD7 LCDD8 LCDD9 LCDD10 LCDD11 LCDD12 LCDD13 LCDD14
Relation between LCD group register and LCD display dot
LCD group register Address Bit Symbol m b7 b6 b5 b4 b3 b2 b1 b0 f b e g d c a -
x
LCD segment register Bit b3 b2 b1 b0 b3 b2 b1 b0
COM1 pin f
b3
e
b1
d
b3
a
b1
COM0 pin b
b2
g
b0
c
b2 b0
LCDn-3 pin LCDn-2 pin LCDn-1 pin LCDn pin
363
PD17010
21.3.4 Function of LCD group register The LCD group register sets the data of the LCD display dot that is to be illuminated or extinguished, like the LCD segment register. As shown in Figure 21-6, data is set to the LCD group register in 7-dot or 4-dot units via data buffer. By executing the "PUT LCDRn, DBF" instruction, therefore, the LCD display data of a group specified by "n" (0 n 7) is set. If the "PUT LCDRn, DBF" instruction is executed at this time, the corresponding value of the LCD segment register is changed accordingly. In other words, display data of 7 dots can be set with a single instruction by using the LCD group register. The LCD segment register sets output data when the segment signal output pin is used as an output port pin. The following 21.3.5 describes the relation between the LCD group register and data buffer. Because the LCD group register can set display data of 7 dots with one instruction, it can be used to display a 7segment LCD wired as shown below.
COM1 a f g e d LCD3 LCD2 LCD1 LCD0 c COM0 b
The configuration and function of each LCD group register are described next.
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PD17010
Name Symbol Address Bit Data DBF3 0CH Data Buffer DBF2 0DH DBF1 0EH DBF0 0FH
b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 Don't care Don't care Transfer data GET reads undefined data PUT can be executed Peripheral Register Name LCD group register 0 b7 b6 b5 b4 b3 b2 b1 b0 Valid data - Symbol LCDR0
Peripheral address
8
Peripheral hardware LCD segment group 0 LCD segment group 1 LCD segment group 2 LCD segment group 3 LCD segment group 4 LCD segment group 5 LCD segment group 6 LCD segment group 7
08H
LCD group register 1
-
-
-
-
LCDR1
09H
LCD group register 2
-
LCDR2
0AH
LCD group register 3
-
LCDR3
0BH
LCD group register 4
-
LCDR4
0CH
LCD group register 5
-
-
-
-
-
LCDR5
0DH
LCD group register 6
-
LCDR6
0EH
LCD group register 7
-
LCDR7
0FH
Don't care
Illuminates or extinguishes each dot (segment) of LCD display Segment a Segment c Segment d Segment g Segment e Segment b Segment f 0 1 Extinguished llluminated
For the relation among segments a through g and each dot, refer to Figure 21-7.
365
PD17010
Figure 21-7. Relation among LCD Display Dot, Ports 0E Through 0Y, Key Source Output, and Data Setting Registers (1/2)
Key source data register Key source (peripheral address) Bit P0X, P0Y group registers (peripheral address) Generalpurpose port Bit Port register (RAM address) Bit P0F (6DH) b3 b2 b1 b0 P0E (6BH) b3 b2 b1 b0 P0X (0CH) b7 b6 b5 b4 b3 b2 b1 b0 P0XH (69H) P0XL (68H)
b3 b2 b1 b0 b3 b2 b1 b0
P 0 F 3
P 0 F 2
P 0 F 1
P 0 F 0
P 0 E 3
P 0 E 2
P 0 E 1
P 0 E 0
P 0 X 5
P 0 X 4
P 0 X 3
P 0 X 2
P 0 X 1
P 0 X 0
LCD group 7 COM1 pin (43) b3 f b2 b b1 e b0 g b3 d b2 c b1 a b0 b3 f b2 b
LCD group 6 b1 e b0 g b3 d b2 c b1 a b0
LCD group 5 b3 d b2 c b1 a b0 b3 f b2 b
LCD group 4 b1 e b0 g b3 d b2 c b1 a b0
COM0 pin (44)
L C D 29 Pin No. Bit LCD segment register (RAM address) Bit LCD group register (peripheral address) f (45)
L C D 28 (46)
L C D 27 (47)
L C D 26 (48)
L C D 25 (49)
L C D 24 (50)
L C D 23 (51)
L C D 22 (52)
L C D 21 (53)
L C D 20 (54)
L C D 19 (55)
L C D 18 (56)
L C D 17 (57)
L C D 16 (58)
b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 LCDD14 (6EH) b e g d LCDD13 (6DH) c a f LCDD12 (6CH) b e g d LCDD11 (6BH) c a LCDD10 (6AH) f LCDD9 (69H) b e g d LCDD8 (68H) c a -
LCD function
LCDR7 (0FH)
LCDR6 (0EH)
LCDR4 (0CH)
-
-
-
-
d
c
a
-
LCDR5 (0DH)
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PD17010
Figure 21-7. Relation among LCD Display Dot, Ports 0E Through 0Y, Key Source Output, and Data Setting Registers (2/2)
KSR (42H) b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 P0Y (42H) b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
P 0 Y 15 / K S 15
P 0 Y 14 / K S 14
P 0 Y 13 / K S 13
P 0 Y 12 / K S 12
P 0 Y 11 / K S 11
P 0 Y 10 / K S 10
P 0 Y 9 / K S 9
P 0 Y 8 / K S 8
P 0 Y 7 / K S 7
P 0 Y 6 / K S 6
P 0 Y 5 / K S 5
P 0 Y 4 / K S 4
P 0 Y 3 / K S 3
P 0 Y 2 / K S 2
P 0 Y 1 / K S 1
P 0 Y 0 / K S 0
LCD group 3 b3 f b2 b b1 e b0 g b3 d b2 c b1 a b0 b3 f b2 b
LCD group 2 b1 e b0 g b3 d b2 c b1 a b0
LCD group 1 b3 e b2 g b1 f b0 c b3 b1 b3 f b2 b
LCD group 0 b1 e b0 g b3 d b2 c b1 a b0 Bit correspondence of segment register Segment correspondence of register
b2
b0
L C D 15 (59)
L C D 14 (60)
L C D 13 (61)
L C D 12 (62)
L C D 11 (63)
L C D 10 (64)
L C D 9 (65)
L C D 8 (66)
L C D 7 (67)
L C D 6 (68)
L C D 5 (69)
L C D 4 (70)
L C D 3 (71)
L C D 2 (72)
L C D 1 (73)
L C D 0 (74)
b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 LCDD7 (67H) f b e g d LCDD6 (66H) c a f LCDD5 (65H) b e g d LCDD4 (64H) c a LCDD3 (63H) LCDD2 (62H) f LCDD1 (61H) d e g d LCDD0 (60H) c a -
LCDR3 (0BH)
LCDR2 (0AH)
LCDR0 (08H)
f
-
e
g
-
c
-
-
LCDR1 (09H)
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PD17010
21.4 Output Timing Control Block and Segment/Port Select Block
21.4.1 Configuration of output timing control block and segment/port select block Figure 21-8 shows the configuration of the common and segment signal/key source signal output timing control blocks and segment signal/general-purpose output port select block. Figure 21-8. Configuration of Timing Control Block and Port Select Block
Control Register 10H Address 11H Bit b3 b2 b1 b0 b3 b2 b1 PPPP00K S 0000 Flag E YXEF N symbol S S S S EEEE LLLL
b0 L C D E N
VDD Port data LCD0/P0Y0/KS0
1 0
Segment signal/ key source signal timing control
Key source data register b0 LCD segment register b1
LCD15/P0Y15/KS15 LCD16/P0X5 LCD26/P0F0 LCD27/P0F1
VDD
LCD28/P0F2
1 0
Port data
Segment signal timing control
b0 LCD segment register b1
VDD
LCD29/P0F3
1 0
Port data
Segment signal timing control
b2 LCD segment register b3
Basic clock for timing control
VDD
VDD
COM0 Common signal timing control
COM1
368
PD17010
21.4.2 Function of segment signal/general-purpose output port select block The segment signal/general-purpose output port select block specifies whether each pin is used as a segment signal output pin or a general-purpose output port pin, by using the P0YSEL through P0FSEL flags of the LCD port select register. When each flag is "1", the corresponding pin is specified as a general-purpose output port pin. Segment pins that are not used as general-purpose output ports can be used to perform LCD display. Although the LCD15/P0Y15/KS15 through LCD0/P0Y0/KS0 pins can output segment signals and key source signals at the same time, port output takes precedence when port 0Y is selected. For the details of the general-purpose output port, refer to 15. GENERAL-PURPOSE PORTS. The following 21.4.4 describes the configuration and function of the LCD port select register. 21.4.3 Function of output timing control block The output timing control block controls the timing of the common and segment signals for LCD display and the timing of the key source and segment signals when the key source controller/decoder is used. The common and segment signals are output when the LCDEN flag of the LCD mode select register is set to "1". In other words, the LCD display can be turned off by the LCDEN flag. When the LCD display is turned off, the common and segment signals output low level. The key source signal is output when the KSEN flag of the LCD mode select register is "1". Therefore, use of the key source signal can be specified by the KSEN flag. 21.4.5 describes the configuration and function of the LCD mode select register. 21.4.6 describes the output waveforms of the common and segment signals. For the details of the key source controller/decoder, refer to 22. KEY SOURCE CONTROLLER/DECODER.
369
PD17010
21.4.4 Configuration and function of LCD port select register The LCD port select register specifies whether the LCD segment signal output pins are used as general-purpose output port pins. The configuration and function of this register are illustrated below.
Flag Symbol Name b3 P 0 LCD port select register (LCDPORT) Y S E L b2 P 0 X S E L b1 P 0 E S E L b0 P 0 F S E L 11H Address
Read/ Write
R/W
Selects LCD segment signal output pin or general-purpose output port pin 0 1 Uses LCD26/P0F0-LCD29/P0F3 pins as LCD segment pins Uses LCD26/P0F0-LCD29/P0F3 pins as general-purpose port pins
Selects LCD segment signal output pin or general-purpose output port pin 0 1 Uses LCD22/P0E0-LCD25/P0E3 pins as LCD segment pins Uses LCD22/P0E0-LCD25/P0E3 pins as general-purpose port pins
Selects LCD segment signal output pin or general-purpose output port pin 0 1 Uses LCD16/P0X0-LCD21/P0X5 pins as LCD segment pins Uses LCD16/P0X0-LCD21/P0X5 pins as general-purpose port pins
Selects LCD segment signal output pin or general-purpose output port pin 0 1 Uses LCD0/P0Y0/KS0-LCD15/P0Y15/KS15 pins as LCD segment pins Uses LCD0/P0Y0/KS0-LCD15/P0Y15/KS15 pins as general-purpose port pins
On reset
Power-ON Clock stop CE
0 0
0 0
0 0
0 0
Retained
370
PD17010
21.4.5 Configuration and function of LCD mode select register (LCDMODE) The LCD mode select register turns ON/OFF LCD display and specifies output of the key source signals. The configuration and function of this register are illustrated below.
Flag Symbol Name b3 b2 b1 K LCD mode select register (LCDMODE) S 0 0 E N b0 L C D E N 10H Address
Read/ Write
R/W
Turns ON/OFF all LCD display 0 1 Display OFF (segment and common output pins output low level) Display ON
Sets output of key source signal 0 1 Key source OFF Key source ON
Fixed to "0"
On reset
Power-ON Clock stop CE
0
0
0 0
0 0
Retained
371
PD17010
21.4.6 Output waveforms of common and segment signals Figures 21-9 and 21-10 show the output waveforms of the common and segment signals. Figure 21-9 shows the waveform when the key source signals are not output, and Figure 21-10 shows the waveform when the key source signals are output. As shown in Figure 21-9, the LCD driver outputs a 1/2-duty, 1/2-bias signal (voltage average method) with a frame frequency of 250 Hz. As the common signals, the COM1 and COM0 pins output three levels of voltages (0, 1/2VDD, VDD) each having a phase different of 1/4 from the others. Therefore, voltages in a range of 1/2VDD are output as the common signal. This method is called 1/2 bias driving method. As the segment signals, two levels of voltages (0, VDD) having a phase corresponding to the display dot are output from the segment signal output pins. Because two display dots are illuminated or extinguished by one segment pin as shown in Figure 21-9, four types of phase differences, <1> through <4> in Figure 21-9, are output to dots A and B, by using combination of ON and OFF statuses. Dots A and B light when the phase difference between the common and segment signals reaches VDD. The duty factor at which each of dots A and B lights is 1/2 and the frequency is 250 Hz. This display method is called 1/2 duty driving method, and the frequency is called frame frequency. Figure 21-9. Output Waveforms of Common and Segment Signals (when key source signals are not output)
COM1 pin COM0 pin Dot A Dot B Output pin of each segment signal (LCDn)
Common signal
COM1 pin VDD 1/2VDD GND COM0 pin VDD 1/2VDD GND Each segment pin <1>A = off, B = off
<2> A = on, B = off A = on <3> A = off, B = on B = on <4> A = on, B = on A = on 2 ms B = on 2 ms A = on 2 ms B = on 2 ms A = on 2 ms B = on 2 ms B = on B = on A = on A = on
372
PD17010
Figure 21-10. Output Waveforms of Common and Segment Signals (when key source signals are output)
COM1 pin COM0 pin
Dot A Dot B Output pin of each segment signal (LCDn)
Common signal COM1 pin VDD 1/2VDD GND COM0 pin VDD 1/2VDD GND
Each segment pin ("1" is output as key source)
<1>A = off, B = off
<2> A = on, B = off A = on <3> A = off, B = on B = on <4> A = on, B = on A = on B = on A = on B = on A = on B = on B = on B = on A = on A = on
Each segment pin ("0" is output as key source) <1>A = off, B = off
<2> A = on, B = off A = on <3> A = off, B = on B = on <4> A = on, B = on A = on 2 ms B = on 2 ms A = on 2 ms B = on 2 ms A = on 2 ms B = on 2 ms B = on B = on A = on A = on
373
PD17010
21.5 Using LCD Controller/Driver
Figure 21-11 shows an example of wiring of an LCD panel. An example of a program that turns on a 7-segment display by using the LCD0 through LCD3 pins and the wiring shown in Figure 21-11 is given below. Example PMNO MEM CH LCDDATA: ; ; DW DW DW DW DW DW DW DW DW DW DW DW DW DW DW DW FLAG 0.01H DBF0.1 ; Preset memory number and BK data storage area ; Symbol definition of least significant bit of DBF as "CH" display flag ; Table data for display b3b2b1b0b3b2b1b0 ; Corresponds to LCD segment register f b egdca- ; Corresponds to LCD group register 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B ; BLANK 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 B ;1 0 0 0 0 0 0 0 0 0 1 1 1 1 0 1 0 B ;2 0 0 0 0 0 0 0 0 0 1 0 1 1 1 1 0 B ;3 0 0 0 0 0 0 0 0 1 1 0 1 0 1 0 0 B ;4 0 0 0 0 0 0 0 0 1 0 0 1 1 1 1 0 B ;5 0 0 0 0 0 0 0 0 1 0 1 1 1 1 1 0 B ;6 0 0 0 0 0 0 0 0 1 1 0 0 0 1 1 0 B ;7 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 B ;8 0 0 0 0 0 0 0 0 1 1 0 1 1 1 1 0 B ;9 0 0 0 0 0 0 0 0 1 1 1 1 1 0 1 0 B ;A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 B ;B 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 B ;C 0 0 0 0 0 0 0 0 1 1 1 0 1 1 1 0 B ;D 0 0 0 0 0 0 0 0 1 0 1 1 1 0 1 0 B ;E 0 0 0 0 0 0 0 0 1 0 1 1 0 0 1 0 B ;F
CLR4 P0YSEL, P0XSEL, P0ESEL, P0FSEL MOV MOV MOV MOV MOV ADD RPL, #1110B AR3, #.DL. LCDDATA SHR 12 AND 0FH AR2, #.DL. LCDDATA SHR 8 AR1, #.DL. LCDDATA SHR 4 AR0, #.DL. LCDDATA AR0, PMNO #0 #0 #0 @AR #0000B #0000B AND 0FH AND 0FH AND 0FH
ADDC AR1, ADDC AR2, ADDC AR3, MOVT DBF, MOV MOV RPH, RPL,
SKGE PMNO, #0AH SET1 CH LD LD LCDD1, DBF1 LCDD0, DBF0
SET1 LCDEN
374
Figure 21-11. Example of Wiring of LCD Panel
A FM MW SW LW e d g c e f a b f
B a b g c d e f
C a b g c d e f
D a b g c d E F G AM PM MHz kHz e d g c CH f a b
CCL OOC MMD
1
0 29
L C D
28
L C D
27
L C D
26
LL CC DD
25 24
L C D
23
LLLLL CCCCC DDDDD
22 21 20 19 18
L C D
17
L C D
16
LL CC DD
15 14
L C D
13
L C D
12
LL CC DD
11 10
L C D
9
LL CC DD
87
LL CC DD
65
LLL CCC DDD
432
L C D
1
L C D
0
Correspondence among Segment Pins, Common Pins, and LCD Panel Display
Segment pin
L C D
29
L C D
28
L C D
27
L C D
26
L C D
25
L C D
24
L C D
23
L C D
22
L C D
21
L C D
20
L C D
19
L C D
18
L C D
17
L C D
16
L C D
15
L C D
14
L C D
13
L C D
12
L C D
11
L C D
10
L C D
9
L C D
8
L C D
7
L C D
6
L C D
5
L C D
4
L C D
3
L C D
2
L C D
1
L C D
0
Common pin COM1
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
PD17010
43 FM MW
f
e
d
a
A
f
e
d
a
f
e
d
a
f
e
d
a
F
E
PM AM
f
e
d
a
COM0
44 SW LW
b
g
c
B
b
g
c
:
b
g
c
C
b
g
c
D
G kHz MHz b
g
c
CH
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21.6 Reset Status
21.6.1 On power-ON reset The LCD29/P0F3 through LCD0/P0Y0/KS0 pins are specified as the LCD segment signal output pins, and output a low level. The COM1 and COM0 pins output a low level. Therefore, the LCD display is turned off. 21.6.2 On execution of clock stop instruction The LCD29/P0F3 through LCD0/P0Y0/KS0 pins are specified as the LCD segment signal output pins, and output a low level. The COM1 and COM0 pins output a low level. Therefore, the LCD display is turned off. 21.6.3 On CE reset Of the LCD29/P0F3 through LCD0/P0Y0/KS0 pins, those that are specified as segment signal output pins output segment signals and those that are specified as general-purpose output port pins retain the output values. The COM1 and COM0 pins output the common signals. 21.6.4 In halt status Of the LCD29/P0F3 through LCD0/P0Y0/KS0 pins, those that are specified as segment signal output pins output segment signals and those that are specified as general-purpose output port pins retain the output values. The COM1 and COM0 pins output the common signals.
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22. KEY SOURCE CONTROLLER/DECODER
The key source controller/decoder can configure a key matrix consisting of up to 64 keys by outputting LCD segment signals and key source signals by means of time division.
22.1 Configuration of Key Source Controller/Decoder
Figure 22-1 shows the configuration of the key source controller/decoder. As shown in this figure, the key source controller/decoder consists of a segment signal/key source signal timing output control block, a segment signal/output port select block, a key source data register, a key input control block, and a P0D port register. 22.2 outlines the function of each block. Figure 22-1. Block Diagram of Key Source Controller/Decoder
Control register
Data buffer
Key source data register (KSR) 16 P0D port register (data memory)
LCD display data
Key source data latch
Segment signal/key source signal output timing control
Segment signal/output port select
Key input control
L C D 15 / P 0 Y 15 / K S 15
L C D 14 / P 0 Y 14 / K S 14
L C D 2 / P 0 Y 2 / K S 2
L C D 1 / P 0 Y 1 / K S 1
L C D 0 / P 0 Y 0 / K S 0
P 0 D 3 / A D C 5
P 0 D 2 / A D C 4
P 0 D 1 / A D C 3
P 0 D 0 / A D C 2
Key matrix
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22.2 Functional Outline of Key Source Controller/Decoder
The key source controller/decoder can configure a key matrix of up to 64 keys by using the key source signal output pins (LCD15/P0Y15/KS15 through LCD0/P0Y0/KS0 pins) and key input pins (P0D3/ADC5 through P0D0/ADC2 pins). Figure 22-2 shows an example of configuration of a key matrix. The LCD15/P0Y15/KS15 through LCD0/P0Y0/KS0 pins are shared with LCD segment signal output pins. Therefore, these pins output key source signals and LCD segment signals by means of time division. The following 22.2.1 through 22.2.4 outline the function of each block of the key source controller/decoder. Figure 22-2. Example of Key Matrix Configuration
Key source output pin
Key input pin
22.2.1 Key source data register (KSR) The key source data register sets the key source output data of the pin that outputs a key source signal. Data are set to this register via data buffer. When data are set to this register, the key source data are output from the LCD15/P0Y15/KS15 through LCD0/P0Y0/ KS0 pins. The key source data register also sets output data when the LCD15/P0Y15/KS15 through LCD0/P0Y0/KS0 pins are used as general-purpose output port pins. When data are set to the key source data register, the port output data are output from the corresponding pins. For details, refer to 22.3. 22.2.2 Segment signal/key source signal output timing control block The segment signal/key source signal output timing control block controls the timing of the key source and segment signals output from the LCD29/P0F3 through LCD0/P0Y0/KS0 pins. Whether the key source signals are used or not is specified by the LCD mode select register. The key source signals are not output when the LCD display is not used. At this time, these pins output a low level. Whether the LCD display is used or not is specified by the LCD mode select register. For details, refer to 22.4.
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PD17010
22.2.3 Segment signal/general-purpose port select block The segment signal/general-purpose port select block selects whether the LCD29/P0F3 through LCD0/P0Y0/KS0 pins are used for LCD display (segment signal output) or as general-purpose output port pins. Whether the segment signal output or general-purpose output port pin is used is specified by the LCD port select register. To output the key source signals, the LCD29/P0F3 through LCD0/P0Y0/KS0 pins must be specified as the LCD signal output pins. For details, refer to 22.4. 22.2.4 Key input control block and P0D port register The key input control block detects the key signals input to the P0D3/ADC5 through P0D0/ADC2 pins in synchronization with the key source signal output timing. Therefore, to output the key source signals from the LCD15/P0Y15/KS15 through LCD0/P0Y0/KS0 pins, the P0D3/ ADC5 through P0D0/ADC2 pins are used as key input pins. The key input data are read by the P0D port register (address 73H of BANK0) on the data memory. Because the P0D3/ADC5 through P0D0/ADC2 pins are multiplexed with the A/D converter pins, care must be exercised when using these pins as the A/D converter pins. For details, refer to 22.5.
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22.3 Key Source Data Setting Block
22.3.1 Configuration of key source data setting block Figure 22-3 shows the configuration of the key source data setting block. Figure 22-3. Configuration of Key Source Data Setting Block
Address Symbol Data
Data Buffer (DBF) 0CH 0DH 0EH DBF3 DBF2 DBF1 M S B 16
0FH DBF0 L S B Peripheral address 42H
Key source data register (KSR)
Key source data latch
22.3.2 Function of key source data setting block The key source data setting block sets the key source data output from the LCD15/P0Y15/KS15 through LCD0/P0Y0/ KS0 pins. The key source data is set by the key source data register (KSR: peripheral address 42H) via data buffer. Each bit of the key source data register corresponds to each of the LCD15/P0Y15/KS15 through LCD0/P0Y0/KS0 pins, and sets the key source data of each pin. The pin that is set to "1" by the key source data register outputs a high level as the key source signal. The pin that is reset to "0" outputs a low level. For the output timing, refer to 22.4. When the LCD15/P0Y15/KS15 through LCD0/P0Y0/KS0 pins are used as general-purpose output port pins, this block sets the output data. The register that sets the data at this time is called the P0Y group register (P0Y: peripheral address 42H). The peripheral address of this register is the same as that of the key source data register. The only difference is the name. The following 22.3.3 describes the configuration and function of the key source data register. Also refer to Figure 21-7 in 21. LCD CONTROLLER/DRIVER.
380
PD17010
22.3.3 Configuration and function of key source data register (KSR) The configuration and function of the key source data register are illustrated below.
Name Symbol Address Bit Data DBF3 0CH
Data Buffer DBF2 0DH DBF1 0EH DBF0 0FH
b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 b3 b2 b1 b0 Transfer data GET can be executed PUT can be executed Peripheral Register
16
Name Key source data register
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Valid data
Symbol KSR
Peripheral address
Peripheral hardware Key source controller/decoder
42H
Specifies key source signal output pin LCD0/P0Y0/KS0 pin LCD1/P0Y1/KS1 pin LCD2/P0Y2/KS2 pin LCD3/P0Y3/KS3 pin LCD4/P0Y4/KS4 pin LCD5/P0Y5/KS5 pin LCD6/P0Y6/KS6 pin LCD7/P0Y7/KS7 pin LCD8/P0Y8/KS8 pin LCD9/P0Y9/KS9 pin LCD10/P0Y10/KS10 pin LCD11/P0Y11/KS11 pin LCD12/P0Y12/KS12 pin LCD13/P0Y13/KS13 pin LCD14/P0Y14/KS14 pin LCD15/P0Y15/KS15 pin 0 1 Does not output key source signal Outputs key source signal
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PD17010
22.4 Output Timing Control Block and Segment/Port Select Block
22.4.1 Configuration of output timing control block and segment/port select block Figure 22-4 shows the common signal and segment signal/key source signal output timing control blocks and segment signal/general-purpose output port select block. Figure 22-4. Configuration of Timing Control Block and Port Select Block
Control Register Address Bit b3 P 0 Flag symbol Y S E L 11H b2 P 0 X S E L b1 P 0 E S E L b0 P 0 F S E L 0 0 b3 10H b2 b1 K S E N b0 L C D E N
VDD
1 LCD0/P0Y0/KS0 0
General-purpose port data
Key source data
Key source data register
Segment signal/ key source signal timing control
b0 b1
LCD segment register
LCD15/P0Y15/KS15 Basic clock for timing control
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PD17010
22.4.2 Function of segment signal/general-purpose output port select block The segment signal/general-purpose output port select block specifies whether the LCD15/P0Y15/KS15 through LCD0/P0Y0/KS0 pins are used as segment signal output pins or general-purpose output port (port 0Y) pins, by using the P0YSEL flag of the LCD port select register. When the P0YSEL flag is "1", these pins are used as general-purpose output port pins. To output key source signals from the LCD15/P0Y15/KS15 through LCD0/P0Y0/KS0 pins, the P0YSEL flag must be reset to "0". When port 0Y is selected, the port output takes precedence. For the details of the general-purpose output port, refer to 15. GENERAL-PURPOSE PORTS. 22.4.3 Function of output timing control block The output timing control block controls the timing of the key source and segment signals. The LCD segment signals are output when the LCDEN flag of the LCD mode select register is "1". The LCD display is turned off when the LCDEN flag is reset to "0". At this time, the segment signal pins output a low level, and the key source signals are not output. To output the key source signals, therefore, the LCDEN flag must be "1". The key source signals are output when the KSEN flag of the LCD mode select register is "1". Therefore, whether the key source signals are used or not is specified by the KSEN flag. To output the key source signals, therefore, the P0YSEL flag must be "0" and, at the same time, the LCDEN and KSEN flags must be "1". The following 22.4.4 describes the configuration and function of the LCD mode select register. 22.4.5 describes the output waveforms of the key source signals and segment signals. For the relation among the common and segment signals of the LCD, and key source signals, refer to 21. LCD CONTROLLER/DRIVER.
383
PD17010
22.4.4 Configuration and function of LCD mode select register (LCDMODE) The LCD mode select register turns ON/OFF LCD display and specifies output of the key source signals. The configuration and function of this register are illustrated below.
Flag Symbol Name b3 b2 b1 K LCD mode select register (LCDMODE) S 0 0 E N b0 L C D E N 10H Address
Read/ Write
R/W
Turns ON/OFF all LCD display 0 1 Display OFF (segment and common output pins output low level) Display ON
Sets output of key source signal 0 1 Key source OFF Key source ON
Fixed to "0"
On reset
Power-ON Clock stop CE
0
0
0 0
0 0
Retained
22.4.5 Output waveforms of segment and key source signals Figure 22-5 shows the output waveforms of the key source and segment signals. As shown in this figure, the key source and segment signals are output by means of time division. The key source signal is output for 220 s at intervals of 4 ms. The pin which is set to "1" by the key source register outputs a high level for 220 s every 4 ms, and the pin which is reset to "0" by the key source register outputs a low level for 220 s every 4 ms. When output of the key source signal is specified (KSEN flag = 1), the pins that do not output key sources (LCD29/ P0F3 through LCD16/P0X0 pins) output the waveform shown in Figure 22-5. However, waveform of "0" is output as the key source data.
384
PD17010
Figure 22-5. Output Waveforms of Key Source and Segment Signals
Dot A Dot B Segment signal Key source signal
COM1 pin COM0 pin
Output pin of each segment/key source signal (LCDn/KSn)
Common signal COM1 pin VDD 1/2VDD GND COM0 pin VDD 1/2VDD GND
Each segment pin ("1" is output as key source) <1>A = off, B = off
<2> A = on, B = off A = on <3> A = off, B = on B = on <4> A = on, B = on A = on B = on A = on B = on A = on B = on B = on B = on A = on A = on
Each segment pin ("0" is output as key source) <1>A = off, B = off
<2> A = on, B = off A = on <3> A = off, B = on B = on <4> A = on, B = on A = on Key source signal 220 s 2 ms 2 ms 2 ms 2 ms 2 ms 2 ms B = on A = on B = on A = on B = on B = on B = on A = on A = on
385
PD17010
22.5 Key Input Block
22.5.1 Configuration of key input block Figure 22-6 shows the configuration of the key input block. Figure 22-6. Configuration of Key Input Control Block
Control Register 16H Bit b3 b2 b1 b0 K Flag E symbol 0 0 0 Y J
Address
VDD A/D converter P0D3/ADC5
1 0 Input latch
Write instruction Port register (1 bit) Read instruction
Segment signal/ key source signal output timing control
KEYJ FF
Read & Reset
Key source timing signal High ON resistance ADC channel select signal P0D2/ADC4 P0D1/ADC3 P0D0/ADC2
Halt release signal
22.5.2 Function of key input control block The key input control block controls the timing to read the key input signals from the P0D3/ADC5 through P0D0/ ADC2 pins and reads key input data. Figure 22-7 shows the key source signals and key input timing. As shown in this figure, the internal pull-down resistor of the P0D3/ADC5 through P0D0/ADC2 pins are off while the display data of the LCD segment is output, and on for only 220 s while the key source signals are output. The signal input to each key input pin is connected to the input latch for 220 s during which the key source signals are output. Therefore, the signal input to each key input pin can be detected during the period of 220 s in which the key source signals are output. Figure 22-8 shows the timing chart of the key source signals, key input signals, and key input data (P0D port register). Whether the key source signals are output or not is detected by the KEYJ flag of the key input judge register (KEYJDG: RF address 16H). The KEYJ flag is set after the key source signals have been output for 220 s, and is reset when data has been set to the key source data register or the content of the KEYJ flag has been read. Therefore, the key input can be loaded by detecting the KEYJ flag after the key source signal data has been output to the key source data register, and detecting the status of each key input pin after the KEYJ flag has been set to "1". The following subsection 22.5.3 describes the configuration and function of the key input judge register.
386
PD17010
Figure 22-7. Key Source Signal and Key Input Timing
COM1 pin COM0 pin Dot A Dot B Segment signal Key source signal
Each segment/key source signal output pin (LCDn/KSn)
Each segment pin (pin outputting "1" to key source. A = on, B = off)
H Segment pin L Pull down Key input pin Open 1 KEYJ flag 0 Key source signal 220 s 2 ms 2 ms
PUT KSR, DBF or SKT1 KEYJ
PUT KSR, DBF or SKT1 KEYJ Signals input to the P0D3/ADC5 through P0D0/ADC2 pins are connected to the input latch during this period. If PUT KSR, DBF is executed during this period, the KEYJ flag is not set for 4 ms. Input data is latched at this point.
Figure 22-8. Timing Chart of Key Source Signal, Key Input Signal, and Key Input Data (P0D Port Register)
H Segment pin L <1> If P0D port register is set to "1" H Key input pin input signal L 1 P0D port register 0 <2> If P0D port register is reset to "0" H Key input pin input signal L 1 P0D port register 0 KEYJ flag is "0" during this period, if value of P0D is read, the status of the P0D pin is read.
Input data is latched at this point.
387
PD17010
22.5.3 Configuration and function of key input judge register The key input judge register detects the presence or absence of a latched key input signal when the LCD segment signal output pins are multiplexed with the key source signal output pins. The configuration and function of this register are illustrated below.
Flag Symbol Name b3 b2 b1 b0 Address
Read/ Write
K Key input judge register (KEYJDG) E 0 0 0 Y J 16H R & Reset
Detects presence/absence of latched key input signal 0 1 Key not latched Key latched
Fixed to "0"
On reset
Power-ON Clock stop CE
0
0
0
0 0 0
The key source signal data is set by setting the contents of the data buffer to the key source data register by using the "PUT" instruction. When the key source signal output data is set by the "PUT" instruction via data buffer, the KEYJ flag is reset to 0. The KEYJ flag is also reset to 0 when it is read to the window register by the "PEEK" instruction (Read & Reset).
388
PD17010
22.6 Using Key Source Controller/Decoder
22.6.1 Configuration of key matrix Figure 22-9 shows an example of key matrix configuration. As shown in this figure, a key matrix can consist of up to 64 keys. Because the key source signal output pins also output LCD segment signals at the same time, diode "A" must be connected to prevent the flowing back of the LCD segment signals when a momentary switch is used. Diodes "B" and "C" are used to prevent sneaking of the key source signal. Use PNP transistors as the transistor switches. The following paragraph (1) describes the points to be noted when NPN transistors are used. Paragraphs (2) through (4) describe the points to be noted when diodes A, B, and C are not used. Figure 22-9. Example of Key Matrix Configuration
A
B
To LCD panel
78
77
76
75
74
73
72
71
70
69
68
67
66
65
60
59
Configuration of each switch
Momentary switch KS K K Alternate switch KS K Diode switch KS
C KS K K or C KS K KS K KS
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PD17010
(1) Note on using a NPN transistor switch If an NPN transistor is used as a transistor switch, a low level may not be correctly read as shown in the example below.
--------------------------------------
In the figure on the left, if KS is low and a high level is input to the base of the transistor, the voltage VK input to K is as follows: VK = RB x (VDD - VBE) RA + RB
VDD High RA Low K Internal resistance RB KS
Because KS is low at this time, a low level must be input to K. However, the voltage input to K changes with RA and RB as shown in the above expression. Therefore, a low level may not be input to K depending on the values of RA and RB.
(2) If diode A is not used A circuit example where diode A is missing is shown below. Suppose that switches SW1 and SW2 are on, that a high level is output from KS15, and that a low level is output from KS14, as shown below. If diode A is missing at this time, the currents I1 and I2 shown by the dotted line will start to flow. Therefore, the high level of KS15 and low level of KS14 are not correctly output because of I2. The result is that the key data of K3 cannot be accurately read. If KS15 and KS14 are used as LCD segment signal output pins, the LCD display does not correctly turn on or off.
SW1
LCD SW2
LCD I1 I2 Low High
K2
K3
KS14
KS15
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PD17010
(3) If diode B is not used A circuit example where diode B is missing is shown below. Suppose that switches SW1, SW2, and SW4 are on, and that a high level is output from KS7, as shown below. If diode B is missing at this time, currents I1 and I2 shown by the dotted line will start to flow. Therefore, a high level is input to K2 because of I2 even when switch SW3 is turned off. Consequently, it judges that SW3 is on.
SW1
SW2
SW3
SW4
I2
I1
High
Low
K2
K3
KS7
KS8
(4) If diode C is missing A circuit example where diode C is missing is shown below. Suppose that switches SW2, SW3, and SW4 are on, and that a high level is output from KS8, as shown below. If diode C is missing at this tie, currents I1, I2, and I3 shown by the dotted line will start to flow. Therefore, a high level is input to K2 because of I2 even when switch SW1 is off, and it judges that SW1 is on. Moreover, the high level of KS8 is not correctly output because of I3.
SW1
SW2
SW3
SW4
I2
I1
I3
Low
K2
K3
KS7
KS8
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PD17010
22.6.2 Inputting from alternate switch and diode switch A program example is given below. Example To read the statuses of the alternate and diode switches of the LCD15/P0Y15/KS15 through LCD8/ P0Y8/KS8 pins to addresses 20H through 27H of BANK0 of the data memory. KS8 KEY_IN KEY_LOAD: CLR1 SET2 MOV MOV MOV MOV MOV MOV MOV MOV KSCAN: PUT LOOP: SKF1 BR BR KCHECK: MOV SET1 ST CLR1 MOV INC ADD ADD SKT1 BR KEY_END: RPL#.DM.KEY_IN SHR 3 AND 0EH IXE KS8, KEY_IN IXE RPL, #0000B IX DBF2, DBF2 DBF3, DBF3 CY KSCAN ; End of input ; Updates value of key source data and, ; scans key again ; Judges if all key source lines are input ; Stores key input data to data memory KEYJ KCHECK Processing A LOOP ; Waits until key input is latched ; Judges if key input is latched KSR, DBF ; Outputs signal of key source data P0YON LCDEN, KSEN DBF3, #0000B DBF2, #0001B DBF1, #0000B DBF0, #0000B IXM, #0000B IXL, #0000B RPH, #0000B RPL, #0000B ; Sets LCD15/P0Y15/KS15-LCD8/P0Y8/KS8 pins ; as LCD segment pins ; Outputs LCD segment and key source signals ; Sets key source data ; Outputs low level from KS8 NIBBLE8 MEM 0.20H 0.73H ; P0D port register
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PD17010
22.6.3 Inputting momentary switch by binary search The key source controller/decoder requires 4 ms to input the key of one key source signal line. To input the keys of 16 key source signals, therefore, it takes 64 ms. Therefore, the binary search method described in (1) and (2) are convenient. (1) Flowchart When KS7 through KS0 are used as key source signals of momentary switch
START Initial setting RA 0000B
AR KSDATA + RA DBF @ AR KSR DBF
; Sets key source controller
; Sets offset address of table storing key source data to RA
; Outputs key source data of offset address specified by RA N
KEYJ = 1? Y RB P0D port register Y RA =RB = 0? N Y RA > 7? N RA RA + RA N RB = 0? Y RA RA + 1
; Waits until data is latched to key input latch (4 ms) ; Saves key input data to RB ; If key input data and RA are "0", no key is input. Inputs all keys again.
; If RA is greater than "7", ends input of one key source, and waits for chattering. ; If RA is less than "7", updates RA and continues binary search.
Y RB = 0? N Chattering wait
DBF KSR KSR DBF
; If there is no key input data, checks all keys again.
; Chattering of 4 ms can be executed even if this chattering wait is missing. ; Inputs key input specified by binary search to RC again and checks it. N
KEYJ = 1? Y RC P0D port register Y RC = 0? N Checking of key data END ; Stores key input data before chattering to RB, data after chattering to RC, ; and key source data to RA. ; If RC = 0, chattering is judged, and inputs from start.
393
PD17010
Example of table data for binary search Shift address (RA) 0000B 0001B 0010B 0011B 0100B 0101B 0110B 0111B 1000B 1001B 1010B 1011B 1100B 1101B 1110B 1111B (2) Program example RA RB RC KEY_IN KSDATA: ; ; ; ; DW DW DW DW DW DW DW DW DW DW DW DW DW DW DW DW KKKKKKKKKKKKKKKK SSSSSSSSSSSSSSSS 1111119876543210 543210 0000000011111111B 0000000011110000B 0000000000001100B 0000000011000000B 0000000000000010B 0000000000001000B 0000000000100000B 0000000010000000B 0000000000000001B 0000000000000010B 0000000000000100B 0000000000001000B 0000000000010000B 0000000000100000B 0000000001000000B 0000000010000000B ; RA=0 ; RA=1 ; RA=2 ; RA=3 ; RA=4 ; RA=5 ; RA=6 ; RA=7 ; RA=8 ; RA=9 ; RA=10 ; RA=11 ; RA=12 ; RA=13 ; RA=14 ; RA=15 MEM MEM MEM MEM 0.1AH 0.1BH 0.1CH 0.73H ; General-purpose work register ; General-purpose work register ; General-purpose work register ; P0D port register Table data (key source data) b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5
b4
b3
b2
b1
b0
394
PD17010
KEY_LOAD: CLR1 SET2 START: MOV KSCAN: MOV MOV MOV MOV MOV ADD ADDC ADDC ADDC MOV MOVT PUT LOOP1: SKF1 BR BR KCHECK: MOV LD SKNE SKE BR BR Key input: SKLT BR RA, #1000B LASTCHK ; Unless one key source selected, ADD SKE ADD BR RA, RA RB, #0000B RA, #0001B KSCAN ; updates value of RA and scans key again ; One key source selected? PRL, #.DM.RB SHR 3 AND 0EH RB, KEY_IN RA, #0000B RB, #0000B Key input START ; No key input at all ; Stores key input data to RB ; All keys are checked? KEYJ KCHECK Processing A LOOP1 ; Waits until key input is latched ; Judges if key input is latched AR3, #.DL.KSDATA SHR 0CH AND 0FH AR2, #.DL.KSDATA SHR 8 AND 0FH AR1, #.DL.KSDATA SHR 4 AND 0FH AR0, #.DL.KSDATA AND 0FH RPL, #.DL. AR0 SHR 3 AND 0EH AR0, RA AR1, #0 AR2, #0 AR3, #0 RPL, #0 DBF, @AR KSR, DBF ; Reads table data ; Outputs signal of key source data RA, #0000B P0YON LCDEN, KSEN ; Sets LCD15/P0Y15/KS15-LCD8/P0Y8/KS8 pins ; as LCD segment pins ; Outputs LCD segment and key source signals
395
PD17010
LASTCHK: MOV SKNE BR LOOP2: SKF1 BR BR KEYDEC: MOV LD SET2 SUB SKT1 BR KEY_END: ; stores key source data to RA, ; key input data before chattering to RB, ; and key input data after chattering to RC, ; respectively. RPL, #.DM.RC SHR 3 AND 0EH RC, KEY_IN CAP, Z RC, RB Z START ; Stores key input data to latch ; Compares key input data after ; chattering wait with key input data ; before chattering wait. ; If they differ KEYJ KEYDEC Processing B LOOP2 ; Waits until key input is latched ; Judges if key input is latched RPL, #0 RB, #0000B START ; Key input of one key source? ; If not, it is judged as chattering
Chattering wait
396
PD17010
22.7 Reset Status
22.7.1 At power-ON reset The LCD29/P0F3 through LCD0/P0Y0/KS0 pins are specified as LCD segment signal output pins, and output a low level (display off). Therefore, low-level key source signals are output. 22.7.2 On execution of clock stop instruction The LCD29/P0F3 through LCD0/P0Y0/KS0 pins are specified as LCD segment signal output pins, and output a low level (display off). Therefore, low-level key source signals are output. 22.7.3 At CE reset If the key source signals are output, the output data are retained. 22.7.4 In halt status If the key source signals are output, the output data are retained as is. If key input is specified as the condition under which the halt status is released, the halt status is released when a high level is input to the P0D3/ADC5 through P0D0/ADC2 pins. However, when the key source controller is used, the halt status is released only by the high level input during 220 s in which the key source data is output. To release the halt status by key input by using the key source controller, do not use the P0D3/ADC5 through P0D0/ ADC2 pins for the A/D converter. For how to release the halt status by key input, refer to 12.4 Halt Function.
397
PD17010
23. PD17010 INSTRUCTION 23.1 Instruction Set
b15 b14-b11 BIN. 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 HEX. 0 1 2 3 4 5 6 7 ADD SUB ADDC SUBC AND XOR OR INC INC MOVT BR CALL RET RETSK EI DI RETI PUSH POP GET PUT PEEK POKE RORC STOP HALT NOP 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 8 9 A B C D E F LD SKE MOV SKNE BR BR BR BR r, m m, #n4 @r, m m, #n4 addr (page 0) addr (page 1) addr (page 2) addr (page 3) ST SKGE MOV SKLT CALL MOV SKT SKF m, r m, #n4 m, @r m, #n4 addr (page 0) m, #n4 m, #n m, #n AR AR DBF, p p, DBF WR, rf rf, WR r s h r, m r, m r, m r, m r, m r, m r, m AR IX DBF, @AR @AR @AR ADD SUB ADDC SUBC AND XOR OR m, #n4 m, #n4 m, #n4 m, #n4 m, #n4 m. #n4 m, #n4 0 1
398
PD17010
23.2 Instruction List
Legend AR ASR addr BANK CMP CY DBF h INTEF INTR INTSK IX MP MPE m mR mC n n4 PAGE PC p pH pL r rf rfR rfC SP s WR (x) : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : Address register Address stack register indicated by stack pointer Program memory address (lower 11 bits) Bank register Compare flag Carry flag Data buffer Halt release condition Interrupt enable flag Register automatically saved to stack when interrupt occurs Interrupt stack register Index register Data memory row address pointer Memory pointer enable flag Data memory address indicated by mR, mC Data memory row address (higher) Data memory column address (lower) Bit position (4 bits) Immediate data (4 bits) Page (bits 12 and 11 of program counter) Program counter Peripheral address Peripheral address (higher 3 bits) Peripheral address (lower 4 bits) General register column address Register file address Register file row address (higher 3 bits) Register file column address (lower 4 bits) Stack pointer Stop release condition Window register Contents addressed by x
399
PD17010
Instruction Addition
Mnemonic ADD
Operand r, m m, #n4 (r) (r) + (m) (m) (m) + n4
Operation op code 00000 10000 00010 10010 00111 00111 00001 10001 00011 10011 00110 10110 00100 10100 00101 10101 n=n, then skip n=0, then skip 11110 11111 01001 01011 11001 11011 00111
Instruction Code Operand mR mR mR mR 000 000 mR mR mR mR mR mR mR mR mR mR mR mR mR mR mR mR 000 mC mC mC mC 1001 1000 mC mC mC mC mC mC mC mC mC mC mC mC mC mC mC mC 0111 r n4 r n4 0000 0000 r n4 r n4 r n4 r n4 r n4 n n n4 n4 n4 n4 r
ADDC
r, m m, #n4
(r) (r) + (m) + CY (m) (m) + n4 + CY AR AR + 1 IX IX + 1 (r) (r) - (m) (m) (m) - n4 (r) (r) - (m) - CY (m) (m) - n4 - CY (r) (r) (m) (m) (r) (r) (m) (m) (r) (r) (m) (m) (m) n4 (m) n4 (m) n4
INC
AR IX
Subtraction
SUB
r, m m, #n4
SUBC
r, m m, #n4
Logical operation
OR
r, m m, #n4
AND
r, m m, #n4
XOR
r, m m, #n4
Judgment
SKT SKF
m, #n m, #n m, #n4 m, #n4 m, #n4 m, #n4 r
CMP 0, if (m) CMP 0, if (m)
Comparison
SKE SKNE SKGE SKLT
(m) - n4, skip if zero (m) - n4, skip if not zero (m) - n4, skip if not borrow (m) - n4, skip if borrow CY (r)b3 (r)b2 (r)b1 (r)b0
Rotation
RORC
Transfer
LD ST MOV
r, m m, r @r, m
(r) (m) (m) (r) if MPE=1: (MP, (r)) (m) if MPE=0: (BANK, mR, (r)) (m)
01000 11000 01010
mR mR mR
mC mC mC
r r r
m, @r
if MPE=1: (m) (MP, (r)) if MPE=0: (m) (BANK, mR, (r))
11010
mR
mC
r
m, #n4 MOVT
(m) n4
11101 00111
mR 000
mC 0001
n4 0000
DBF, @AR SP SP-1, ASR PC, PC AR, DBF (PC), PC ASR, SP SP+1
400
PD17010
Instruction Transfer
Mnemonic PUSH POP PEEK POKE GET PUT
Operand AR AR WR, rf rf, WR DBF, p p, DBF addr
Operation op code SP SP-1, ASR AR AR ASR, SP SP + 1 WR (rf) (rf) WR DBF (p) (p) DBF PC10-0 addr, PAGE 0 PC10-0 addr, PAGE 1 PC10-0 addr, PAGE 2 PC10-0 addr, PAGE 3 00111 00111 00111 00111 00111 00111 01100 01101 01110 01111 00111 11100
Instruction Code Operand 000 000 rfR rfR pH pH 1101 1100 0011 0010 1011 1010 addr 0000 0000 rfC rfC pL pL
Branch
BR
@AR Subroutine CALL addr
PC AR SP SP-1, ASR PC, PC10-0 addr, PAGE 0 SP SP-1, ASR PC, PC AR PC ASR, SP SP + 1 PC ASR, SP SP + 1 and skip PC ASR, INTR INTSK, SP SP + 1 INTEF 1 INTEF 0
000
0100 addr
0000
@AR
00111
000
0101
0000
RET RETSK RETI Interrupt EI DI Others STOP HALT NOP s h
00111 00111 00111 00111 00111 00111 00111 00111
000 001 100 000 001 010 011 100
1110 1110 1110 1111 1111 1111 1111 1111
0000 0000 0000 0000 0000 s h 0000
STOP HALT No operation
23.3 Assembler (AS17K) Embedded Macro Instructions
Legend flag n n <>
: FLG symbol : Bit number : Can be omitted
Mnemonic Operand flag 1, ... flag n flag 1, ... flag n flag 1, ... flag n flag 1, ... flag n flag 1, ... flag n Operation if (flag 1) to (flag n) = all "1", then skip if (flag 1) to (flag n) = all "0", then skip (flag 1) to (flag n) 1 (flag 1) to (flag n) 0 if (flag n) = "0", then (flag n) 1 if (flag n) = "1", then (flag n) 0 INITFLG flag 1, ...<flag n> BANKn if description = NOT flag n, then (flag n) 0 if description = flag n, then (flag n) 1 (BANK) n 0n3 1n4 n 1n4 1n4 1n4 1n4 1n4
Embedded macro
SKTn SKFn SETn CLRn NOTn
401
PD17010
24. PD17010 RESERVED WORDS 24.1 Reserved Word List
24.1.1 System register (SYSREG) Symbol Name AR3 AR2 AR1 AR0 WR BANK IXH MPH MPE IXM MPL IXL RPH RPL PSW BCD CMP CY Z IXE Attribute MEM MEM MEM MEM MEM MEM MEM MEM FLG MEM MEM MEM MEM MEM MEM FLG FLG FLG FLG FLG Value 0.74H 0.75H 0.76H 0.77H 0.78H 0.79H 0.7AH 0.7AH 0.7AH.3 0.7BH 0.7BH 0.7CH 0.7DH 0.7EH 0.7FH 0.7EH.0 0.7FH.3 0.7FH.2 0.7FH.1 0.7FH.0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Bits 15-12 of address register Bits 11-8 of address register Bits 7-4 of address register Bits 3-0 of address register Window register Bank register Index register, high Memory pointer, high Memory pointer enable flag Index register, middle Memory pointer, low Index register, low General register pointer, high General register pointer, low Program status word BCD flag Compare flag Carry flag Zero flag Index enable flag
24.1.2 Data buffer (DBF) Symbol Name DBF3 DBF2 DBF1 DBF0 Attribute MEM MEM MEM MEM Value 0.0CH 0.0DH 0.0EH 0.0FH R/W R/W R/W R/W R/W Bits 15-12 of DBF Bits 11-8 of DBF Bits 7-4 of DBF Bits 3-0 of DBF Description
402
PD17010
24.1.3 LCD segment register Symbol Name LCDD0 LCDD1 LCDD2 LCDD3 LCDD4 LCDD5 LCDD6 LCDD7 LCDD8 LCDD9 Attribute MEM MEM MEM MEM MEM MEM MEM MEM MEM MEM Value 0.60H 0.61H 0.62H 0.63H 0.64H 0.65H 0.66H 0.67H 0.68H 0.69H R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Description LCD segment register LCD segment register LCD segment register LCD segment register LCD segment register LCD segment register LCD segment register LCD segment register LCD segment register LCD segment register
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LCDD10 LCDD11 LCDD12 LCDD13 LCDD14
MEM MEM MEM MEM MEM
0.6AH 0.6BH
R/W R/W R/W R/W R/W
LCD segment register LCD segment register LCD segment register LCD segment register LCD segment register
0.6CH 0.6DH 0.6EH
24.1.4 Port register Symbol Name P0A3 P0A2 P0A1 Attribute FLG FLG FLG Value 0.70H.3 0.70H.2 0.70H.1 R/W R/W R/W R/W Bit 3 of port 0A Bit 2 of port 0A Bit 1 of port 0A Description
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
P0A0 P0B3 P0B2 P0B1 P0B0 P0C3 P0C2 P0C1 P0C0 P0D3 P0D2 P0D1 P0D0 P0XL3 P0XL2 P0XL1 P0XL0
FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG
0.70H.0 0.71H.3 0.71H.2 0.71H.1 0.71H.0 0.72H.3 0.72H.2 0.72H.1 0.72H.0 0.73H.3 0.73H.2 0.73H.1 0.73H.0 0.68H.3 0.68H.2 0.68H.1 0.68H.0
R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R R/W R/W R/W R/W
Bit 0 of port 0A Bit 3 of port 0B Bit 2 of port 0B Bit 1 of port 0B Bit 0 of port 0B Bit 3 of port 0C Bit 2 of port 0C Bit 1 of port 0C Bit 0 of port 0C Bit 3 of port 0D Bit 2 of port 0D Bit 1 of port 0D Bit 0 of port 0D Bit 1 of port 0X Bit 0 of port 0X Dummy Dummy
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403
PD17010
Symbol Name P0XH3 P0XH2 P0XH1
Attribute FLG FLG FLG
Value 0.69H.3 0.69H.2 0.69H.1
R/W R/W R/W R/W Bit 5 of port 0X Bit 4 of port 0X Bit 3 of port 0X
Description
------------------------------------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- ----------------------------------------------------
P0XH0 P0E3 P0E2 P0E1 P0E0 P0F3 P0F2 P0F1 P0F0 P1A3 P1A2 P1A1 P1A0 P1B3 P1B2 P1B1 P1B0 P1C3 P1C2 P1C1 P1C0 P1D3 P1D2 P1D1 P1D0 P2A3 P2A2 P2A1 P2A0
FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG
0.69H.0 0.6BH.3 0.6BH.2 0.6BH.1 0.6BH.0 0.6DH.3 0.6DH.2 0.6DH.1 0.6DH.0 1.70H.3 1.70H.2 1.70H.1 1.70H.0 1.71H.3 1.71H.2 1.71H.1 1.71H.0 1.72H.3 1.72H.2 1.72H.1 1.72H.0 1.73H.3 1.73H.2 1.73H.1 1.73H.0 2.70H.3 2.70H.2 2.70H.1 2.70H.0
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R R/W R/W R/W R/W
Bit 2 of port 0X Bit 3 of port 0E Bit 2 of port 0E Bit 1 of port 0E Bit 0 of port 0E Bit 3 of port 0F Bit 2 of port 0F Bit 1 of port 0F Bit 0 of port 0F Bit 3 of port 1A Bit 2 of port 1A Bit 1 of port 1A Bit 0 of port 1A Bit 3 of port 1B Bit 2 of port 1B Bit 1 of port 1B Bit 0 of port 1B Bit 3 of port 1C Bit 2 of port 1C Bit 1 of port 1C Bit 0 of port 1C Bit 3 of port 1D Bit 2 of port 1D Bit 1 of port 1D Bit 0 of port 1D Bit 3 of port 2A Bit 2 of port 2A Bit 1 of port 2A Bit 0 of port 2A
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404
PD17010
24.1.5 Register file (control register) Symbol Name SP SIO1TS Attribute MEM FLG Value 0.81H 0.82H.3 R/W R/W R/W Stack pointer SIO1 start flag Description
------------------------------------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- ----------------------------------------------------
SIO1HIZ
FLG
0.82H.2
R/W
SIO1/P0B1 select flag
SIO1CK1 SIO1CK0
FLG FLG
0.82H.1 0.82H.0
R/W R/W R R R R
Bit 1 of SIO1 clock select Bit 0 of SIO1 clock select
IFCGOSTT PLLUL ADCCMP CE SIO0CH SB
FLG FLG FLG FLG FLG FLG
0.84H.0 0.85H.0 0.86H.0 0.87H.0 0.88H.3 0.88H.2
IF counter gate open status flag PLL unlock FF flag ADC judge flag CE pin status flag SIO0 mode select flag
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R/W R/W
I2C bus/serial I/O mode select flag SIO0 clock mode select flag SIO0 TX/RX select flag Basic timer 1 clock select flag Basic timer 1 clock select flag Basic timer 0 clock select flag Basic timer 0 clock select flag
SIO0MS
FLG
0.88H.1
R/W
SIO0TX BTM1CK1 BTM1CK0 BTM0CK1 BTM0CK0 TMCK3 TMCK2 TMCK1 TMCK0 TMOVF TMRPT
FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG
0.88H.0 0.89H.3 0.89H.2 0.89H.1 0.89H.0 0.8CH.3 0.8CH.2 0.8CH.1 0.8CH.0 0.8DH.0 0.8EH.2
R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W
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Timer/counter clock select flag (dummy: 0) Timer/counter clock select flag (dummy: 0) Timer/counter clock select flag Timer/counter clock select flag Timer/counter overflow detect flag 12-bit timer repeat select flag Timer/counter reset flag
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TMRES TMEN
FLG
0.8EH.1
R/W
FLG
0.8EH.0
R/W
Timer/counter enable flag
IGRPSL KSEN
FLG FLG
0.8FH.0 0.90H.1
R/W R/W
Interrupt group select flag Key source decoder enable flag LCD driver enable flag Port 0Y select flag
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LCDEN R0YSEL P0XSEL P0ESEL P0FSEL IFCMD1 IFCMD0 IFCCK1 IFCCK0 PWM2SEL PWM1SEL PWM0SEL CGPSEL
FLG FLG
0.90H.0 0.91H.3
R/W R/W
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FLG FLG
0.91H.2 0.91H.1
R/W R/W
Port 0X select flag Port 0E select flag
FLG FLG FLG
0.91H.0 0.92H.3 0.92H.2
R/W R/W R/W
Port 0F select flag IF counter mode select flag IF counter mode select flag
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FLG FLG
0.92H.1 0.92H.0
R/W R/W
IF counter clock select flag IF counter clock select flag PWM2 select flag PWM1 select flag PWM0 select flag
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FLG FLG FLG
0.93H.3 0.93H.2 0.93H.1
R/W R/W R/W
FLG
0.93H.0
R/W
CGP select flag
405
PD17010
Symbol Name ADCCH3 ADCCH2 ADCCH1
Attribute FLG FLG FLG
Value 0.94H.3 0.94H.2 0.94H.1
R/W R/W R/W R/W
Description AD mode select flag (dummy: 0) AD mode select flag AD mode select flag
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ADCCH0 PLULSEN3 PLULSEN2 PLULSEN1 PLULSEN0 KEYJ BTM0CY SBACK
FLG FLG FLG FLG FLG FLG FLG FLG
0.94H.0 0.95H.3 0.95H.2 0.95H.1 0.95H.0 0.96H.0 0.97H.0 0.98H.3
R/W R/W R/W R/W R/W R R R/W
AD mode select flag PLL unlock sensibility select flag (dummy: 0) PLL unlock sensibility select flag (dummy: 0) PLL unlock sensibility select flag PLL unlock sensibility select flag Key input judge flag Basic timer 0 carry FF status flag I2C bus acknowledge flag
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SIO0NWT
FLG
0.98H.2
R/W
SIO0 not wait flag
SIO0WRQ1
FLG
0.98H.1
R/W
SIO0 wait mode flag
SIO0WRQ0 SIO0WSTT IEG1 IEG0 PLLMD3 PLLMD2 PLLMD1 PLLMD0 IFCSTRT IFCRES P0CGIO SIO0SF8 SIO0SF9 SBSTT
FLG FLG FLG FLG FLG FLG FLG FLG FLG
0.98H.0 0.99H.0 0.9FH.1 0.9FH.0 0.0A1H.3 0.0A1H.2 0.0A1H.1 0.0A1H.0 0.0A3H.1
R/W R R/W R/W R/W R/W R/W R/W R/W
SIO0 wait mode flag SIO0 wait status judge flag INT1 interrupt edge select flag INT0 interrupt edge select flag PLL mode select flag (dummy: 0) PLL mode select flag (dummy: 0) PLL mode select flag PLL mode select flag IF counter start flag
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FLG FLG FLG FLG FLG
0.0A3H.0 0.0A7H.0 0.0A8H.3 0.0A8H.2 0.0A8H.1
R/W R/W R R R
IF counter reset flag Port 0C group I/O select flag SIO0 clock counter status flag SIO0 clock counter status flag I2C bus start condition status flag
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SBBSY IPIFC
FLG FLG
0.0A8H.0 0.0AEH.1
R R/W
I2C bus start/stop condition status flag IF counter interrupt permission flag
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IPSIO0 IPBTM1 IPTM
FLG FLG
0.0AEH.0 0.0AFH.3
R/W R/W
SIO0 interrupt permission flag Basic timer 1 interrupt permission flag 12-bit timer interrupt permission flag
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FLG
0.0AFH.2
R/W
IPGRP IP0
FLG FLG
0.0AFH.1 0.0AFH.0
R/W R/W
Group interrupt permission flag INT0 interrupt permission flag
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PLLRFCK3 PLLRFCK2 PLLRFCK1 PLLRFCK0
FLG FLG FLG FLG
0.0B1H.3 0.0B1H.2 0.0B1H.1 0.0B1H.0
R/W R/W R/W R/W
PLL reference clock select flag PLL reference clock select flag PLL reference clock select flag PLL reference clock select flag
406
PD17010
Symbol Name P1ABIO3 P1ABIO2 P1ABIO1
Attribute FLG FLG FLG
Value 0.0B5H.3 0.0B5H.2 0.0B5H.1
R/W R/W R/W R/W
Description P1A3 I/O select flag P1A2 I/O select flag P1A1 I/O select flag
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P1ABIO0 P0BBIO3 P0BBIO2 P0BBIO1 P0BBIO0 P0ABIO3 P0ABIO2 P0ABIO1 P0ABIO0 SIO0IMD3 SIO0IMD2 SIO0IMD1 SIO0IMD0 SIO0CK3 SIO0CK2 SIO0CK1 SIO0CK0 IRQIFC IRQSIO0 IRQBTM1 IRQTM INT1
FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG FLG
0.0B5H.0 0.0B6H.3 0.0B6H.2 0.0B6H.1 0.0B6H.0 0.0B7H.3 0.0B7H.2 0.0B7H.1 0.0B7H.0 0.0B8H.3 0.0B8H.2 0.0B8H.1 0.0B8H.0 0.0B9H.3 0.0B9H.2 0.0B9H.1 0.0B9H.0 0.0BAH.0 0.0BBH.0 0.0BCH.0 0.0BDH.0 0.0BEH.3
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
P1A0 I/O select flag P0B3 I/O select flag P0B2 I/O select flag P0B1 I/O select flag P0B0 I/O select flag P0A3 I/O select flag P0A2 I/O select flag P0A1 I/O select flag P0A0 I/O select flag SIO0 interrupt mode select flag (dummy: 0) SIO0 interrupt mode select flag (dummy: 0) SIO0 interrupt mode select flag SIO0 interrupt mode select flag SIO0 shift clock select flag (dummy: 0) SIO0 shift clock select flag (dummy: 0) SIO0 shift clock select flag SIO0 shift clock select flag IF counter interrupt request flag SIO0 interrupt request flag Basic timer 1 interrupt request flag 12-bit timer interrupt request flag INT1 pin status flag
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IRQGRP INT0
FLG FLG
0.0BEH.0 0.0BFH.3
R/W R/W
Group interrupt request flag INT0 pin status flag
------------------------------------------------------------------------------------------------------------------------------- ----------------------------------------------------
IRQ0
FLG
0.0BFH.0
R/W
INT0 interrupt request flag
407
PD17010
24.1.6 Peripheral hardware register
Symbol Name ADCR SIO1SFR
Attribute DAT DAT
Value 02H 03H
R/W R/W R/W
Description A/D converter VREF data register SIO1 presettable shift register
------------------------------------------------------------------------------------------------------------------------------- ----------------------------------------------------
SIO0SFR PWMR0 PWMR1 PWMR2 LCDR0 LCDR1 LCDR2 LCDR3 LCDR4 P0X
DAT DAT DAT DAT DAT DAT DAT DAT DAT
04H 05H 06H 07H 08H 09H
R/W R/W R/W R/W W W W W
SIO0 presettable shift register PWM0 data register PWM1 data register PWM2 data register LCD group register 0 LCD group register 1 LCD group register 2 LCD group register 3
------------------------------------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- ----------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- ----------------------------------------------------
0AH 0BH
0CH
W
LCD group register 4
DAT
0CH
W
Port 0X group register
LCDR5 LCDR6 LCDR7 CGPR AR
DAT DAT DAT
0DH 0EH 0FH
W
LCD group register 5
W
LCD group register 6
W R/W R/W
LCD group register 7 CGP data register Address register of GET/PUT/PUSH/POP/CALL/BR/ MOVT/INC instruction
DAT DAT
20H 40H
PLLR KSR P0Y IFC TMM TMC
DAT DAT
41H 42H
R/W R/W
PLL data register Key source data register Port 0Y group register IF counter data register Timer modulo register Timer/counter
------------------------------------------------------------------------------------------------------------------------------- ----------------------------------------------------
DAT DAT DAT DAT
42H 43H 46H 47H
R/W R R/W R
24.1.7 Others Symbol Name DBF IX Attribute DAT DAT Value 0FH 01H Description Fixed operand value of PUT, GET, and MOVT instructions Fixed operand value of INC instruction
408
PD17010
25. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25 2 C) Parameter Supply voltage Input voltage Output voltage Output withstand voltage Symbol VDD VI VO VBDS1 VBDS2 High-level output current IOH Except P1B1-P1B3, P0A2, P0A3 P1B1-P1B3 P0A2, P0A3 1 pin Total of P2A0, LCD0-LCD29 pins Total of all pins except above Low-level output current IOL 1 pin of P0A0-P0A3, P1A1-P1A3, P2A0 1 pin other than above Total of P0A0-P0A3, P1A1-P1A3, P2A0 Total of all pins other than above Total power dissipationNote Operating ambient temperature Storage temperature Tstg -55 to +125 C Pt TA Condition Rating -0.3 to +6.0 -0.3 to VDD +0.3 -0.3 to VDD +0.3 18.0 VDD+0.3 -12 -25 -40 15 10 50 20 450 -40 to +85 Unit V V V V V mA mA mA mA mA mA mA mW C
Note
Refer to Calculation of Total Dissipation on next page.
Caution If the absolute maximum rating of even one of the above parameters is exceeded even momentarily, the product may be damaged. The absolute maximum ratings specify the values which if exceeded may cause the product to be physically damaged. Be sure not to exceed these ratings when using the product. Recommended Operating Range Parameter Supply voltage Symbol VDD1 VDD2 Data retention voltage Supply voltage rise time Input amplitude VDDR trise VIN1 VIN2 Output withstand voltage Operating ambient temperature VBDS TA Condition When PLL and CPU operate When PLL stops and CPU operates When crystal resonator stops VDD = 0 4.5 V VCOL, VCOH AMIFC, FMIFC P1B1-P1B3 -40 0.5 0.5 MIN. TYP. MAX. 4.5 3.5 2.2 5.0 5.0 5.5 5.5 5.5 500 VDD VDD 16.0 +85 Unit V V V ms Vp-p Vp-p V C
409
PD17010
Calculation of Total Dissipation The PD17010 dissipates the following three types of powers, and the sum of these three types of powers must be lower than total dissipation Pt (use at lower than about 80% of the rated dissipation is recommended). <1> CPU dissipation <2> Output pin dissipation : Calculated as VDD (MAX.) x IDD (MAX.) : Total of dissipation when maximum current is allowed to flow into each output pin <3> Dissipation by pull-down resistor : Power dissipation by internal pull-down resistor Here is an example: Example Assume that the following currents flow into the output pins: : 12 mA : 12 mA : 1 mA : 12 mA : 4 mA : 15 mA : 5 mA LCD0 pin LCD1 pin P0B0-P0B2 pins P0B3 pin * Low-level output : P0A0-P0A2 pins P0A3 pin
* High-level output : P2A0 pin
P0C0, P0C1 pins : 10 mA Also assume that a current of 0.3 mA flows into the P0D0 through P0D3 pins with the internal resistor on. <1> CPU dissipation: 5.5 V x 15 mA = 82.5 mW <2> Output pin dissipation : P2A0 pin LCD0 pin LCD1 pin Total of P0B0-P0B2 pins P0B3 pin Total of P0A0-P0A2 pins P0A3 pin Total of P0C0, P0C1 pins ... 2.4 V x 12 mA ... 3 V x 12 mA ... 1 V x 1 mA ... 1 V x 4 mA ... 2 V x 15 mA x 3 ... 2 V x 5 mA ... 2 V x 10 mA x 2 = 28.8 mW = 36 mW = 1 mW = 4 mW = 90 mW = 10 mA = 40 mW
... 2.4 V x 12 mA x 3 = 86.4 mW
<3> Pull-down resistor dissipation: total of P0D0-P0D3 pins ... 5.5 V x 0.3 mA x 4 = 6.6 mW Pt = <1> + <2> + <3> = 82.5 + (28.8 + 36 + 1 + 86.4 + 4 + 90 + 10 + 40) + 6.6 = 385.3 mW Because the absolute maximum value of the total dissipation is 450 mW, it is considered that this rating is not exceeded in the above example. However, design your system taking into consideration the above description.
410
PD17010
DC Characteristics (TA = -40 to +85 C, VDD = 4.5 to 5.5 V) Parameter Supply voltage Supply current Symbol VDD1 VDD2 IDD1 Condition When CPU and PLL operate When CPU operates and PLL stops When CPU and PLL operate TA = 25 C IDD2 When CPU operates and PLL stops When HALT instruction is used (20 instructions are executed every 1 ms) Sine wave input to XIN pin (fIN = 4.5 MHz, VIN = VDD), TA = 25 C Data retention voltage VDDR1 VDDR2 VDDR3 Data retention current IDDR1 IDDR2 Middle-level output voltage High-level input voltage VOM1 VIH1 Power failure detection by timer FF. When crystal resonator is used Power failure detection by timer FF. When crystal resonator stops Retention of data memory (RAM) When crystal resonator stops TA = 25 C When crystal resonator stops VDD = 5.0 V, TA = 25 C COM0, COM1 P1A0-P1A3, P1D0-P1D3 CE, INT0, INT1 VIH2 Low-level input voltage VIL P0D0-P0D3 P0A0-P0A3, P0B0-P0B3, P0C0-P0C3, P0D0-P0D3, P1A0-P1A3, P1D0-P1D3, CE, INT0, INT1 High-level output current IOH1 IOH2 P0A0, P0A1, P1A1-P1A3, P2A0 VOH = VDD - 2 V, VDD = 5 V, TA = 25 C P0B0-P0B3, P0C0-P0C3, P1A0, P1B0, P1C0-P1C3 VOH = VDD -1 V IOH3 Low-level output current IOL1 IOL2 IOL3 IOL4 High-level input current IIH1 IIH2 IIH3 IIH4 Output off leakage current IL1 IL2 IL3 LCD0-LCD29, EO0, EO1 VOH = VDD -1 V -1.0 5.0 1.0 1.0 1.0 0.1 0.1 0.1 0.05 -4.0 15.0 7.0 3.5 2.0 0.8 0.8 1.3 0.13 0.30 500 500 100 mA mA mA mA mA mA mA mA mA nA nA nA P0A0-P0A3, P1A1-P1A3, P2A0 VOL = 2 V, VDD = 5 V, TA = 25 C P0B0-P0B3, P0C0-P0C3, P1B0, P1C0-P1C3 VOL = 1 V LCD0-LCD29, EO0, EO1 P1B1-P1B3 When VCOH pulled down When VCOL pulled down When XIN pulled down P0A2, P0A3 P1B1-P1B3 EO0, EO1 VOL = 1 V VOL = 1 V VIH = VDD VIH = VDD VIH = VDD VOH = VDD VOH = 16 V VOH = VDD, VOL = 0 V -1.0 -5.0 mA -2.0 -10.0 mA 0.6 VDD 0 VDD 0.2 VDD V V VDD = 5 V 2.3 0.8 VDD 2.5 2.7 VDD V V P0A0-P0A3, P0B0-P0B3, P0C0-P0C3, 2.0 2 2 5.5 5 3 V 2.2 5.5 V 3.5 5.5 V 0.45 0.90 mA XIN pin Sine wave input (fIN = 4.5 MHz, VIN = VDD), MIN. 4.5 3.5 TYP. MAX. 5.0 5.0 1.2 5.5 5.5 2.4 Unit V V mA
A A
When P0D0-P0D3 pulled down VIH = VDD
411
PD17010
AC Characteristics (TA = -40 to + 85 C, VDD = 4.5 to 5.5 V) Parameter Operating frequency Symbol fIN1 Condition VCOL MF mode, sine wave input, VIN = 0.2 Vp-p fIN2 VCOL HF mode, sine wave input, VIN = 0.2 Vp-p fIN3 fIN4 fIN5 fIN6 fIN7 AD conversion resolution AD conversion total error TA = -10 to + 50 C 1 VCOH, sine wave input, AMIFC, sine wave input, AMIFC, sine wave input, FMIFC, sine wave input, FMIFC, sine wave input, VIN = 0.2 Vp-p VIN = 0.5 Vp-p VIN = 0.05 Vp-p VIN = 0.5 Vp-p VIN = 0.06 Vp-p 9 0.1 0.44 5 10.5 150 1 0.46 15 10.9 6 1.5 MHz MHz MHz MHz MHz bit LSB 5 40 MHz MIN. 0.5 TYP. MAX. 30 Unit MHz
Reference Characteristics Parameter Supply current Symbol IDD3 Condition When CPU and PLL operate VCOH sine wave input, fIN = 150 MHz, VIN = 0.3 Vp-p VDD = 5 V, TA = 25 C High-level output current Middle-level output current IOH4 IOM1 IOM2 Low-level output current IOL5 COM0, COM1 COM0, COM1 COM0, COM1 COM0, COM1 VOH = VDD -1 V VOM = VDD -1 V VOM = 1 V VOL = 1 V -0.2 -20 20 0.2 mA MIN. TYP. MAX. 15 Unit mA
A A
mA
412
PD17010
26. PACKAGE
(a) Package for mass production
80 PIN PLASTIC QFP (14 20)
A B
64 65
41 40
detail of lead end
C
D
S
80 1
F
25 24
G
H
I
M
J K
P
N
NOTE
L
ITEM A B MILLIMETERS 23.20.2 20.00.2 14.00.2 17.20.2 1.0 1.8 0.350.10 0.15 0.8 (T.P.) 1.60.2 0.80.2 0.15 +0.10 -0.05 0.12 2.7 0.1250.075 55 3.0 MAX. INCHES 0.913 +0.009 -0.008 0.787 +0.009 -0.008 0.551 +0.009 -0.008 0.6770.008 0.039 0.031 0.014 +0.004 -0.005 0.006 0.031 (T.P.) 0.0630.008 0.031 +0.009 -0.008 0.006 +0.004 -0.003 0.005 0.106 0.0050.003 55 0.119 MAX. S80GF-80-3B9-2
Each lead centerline is located within 0.15 mm (0.006 inch) of its true position (T.P.) at maximum material condition.
M
Caution
The ES model is different from the massproduction model in package and materials. Refer to (b) Package of ES model.
C D F G H I J K L M N P Q R S
Q
R
413
PD17010
(b) Package of ES model 80 PIN CERAMIC QFP FOR ES (REFERENCE) (UNIT: mm)
414
PD17010
27. RECOMMENDED SOLDERING CONDITIONS
Solder this product under the following recommended conditions. For the details of the recommended soldering conditions, refer to Information document Semiconductor Device Mounting Technology Manual (IEI-1207). For the soldering methods and conditions other than those recommended, consult NEC. Table 27-1. Soldering Conditions of Surface Mount Type
PD17010GF-xxx-3B9: 80-pin plastic QFP (14 x 20 mm) PD17010GF-Exx-3B9: 80-pin plastic QFP (14 x 20 mm)
Symbol of Recommended Condition IR35-207-2
Soldering Method Infrared reflow
Soldering Condition Package peak temperature: 235 C, Time: 30 seconds MAX. (210 C MIN.), Number of times: 2 MAX., Number of days: 7 (After this, 20 hours of prebaking is necessary at 125 C.) (1) Start second reflow after the device temperature that has risen due to the first reflow has dropped to room temperature. (2) Do not clean flux with water after the first reflow. Package peak temperature: 215 C, Time: 40 seconds MAX. (200 C MIN.), Number of times: 2 MAX., Number of days: 7 (After this, 20 hours of prebaking is necessary at 125 C.) (1) Start second reflow after the device temperature that has risen due to the first reflow has dropped to room temperature. (2) Do not clean flux with water after the first reflow. Soldering bath temperature: 260 C MAX., Time: 10 seconds MAX., Number of times: 1, Preheating temperature: 120 C MAX. (package surface temperature), Number of days: 7Note (After this, 20 hours of prebaking is necessary at 125 C.) Pin temperature: 300 C MAX., Time: 3 seconds MAX. (per side of device)
Note Note
VPS
VP15-207-2
Wave soldering
WS60-207-1
Pin partial heating
--
Note
Number of days for storage after the dry pack was opened. The storage conditions are at 25 C, 65% RH MAX.
Caution Do not use two or more soldering methods in combination (except pin partial heating).
415
PD17010
APPENDIX A. NOTES ON CONNECTING CRYSTAL RESONATOR
When connecting a crystal resonator, wire the portion enclosed by a dotted line in Figure A-1 below as follows to prevent the adverse influence of the circuit capacitance: * Keep the wiring length as short as possible. * Do not cross the wiring with any other signal lines. Do not route the wiring in the vicinity of lines through which a high alternating current flows. * Keep the ground point of the capacitor of the oscillation circuit at the same potential as GND. Do not ground the circuit to a ground pattern through which a high current flows. * Do not extract signals from the oscillation circuit. When connecting the capacitor or adjusting the oscillation frequency, keep in mind the following points (1) through (3): (1) If the capacitances C1 and C2 are too high, the oscillation characteristics may be degraded and the current dissipation may increase. (2) Generally, connect the trimmer capacitor for oscillation frequency adjustment to the XIN pin. However, depending on the crystal resonator to be used, the oscillation stability may be degraded if the trimmer capacitor is connected to the XIN pin (in this case, connect the trimmer capacitor to the XOUT pin). Therefore, evaluate oscillation by using the crystal resonator actually used. (3) Adjust the oscillation frequency by measuring the LCD drive waveform (125 Hz) or VCO oscillation frequency. If a probe is connected to the XOUT or XIN pin, accurate measurement cannot be made due to the capacitance of the probe. Figure A-1. Connecting Crystal Resonator
PD17010
XOUT
XIN
4.5-MHz crystal resonator
C1
C2
416
PD17010
APPENDIX B. DIFFERENCES AMONG PD17010, PD17003A, AND PD17005
(1) Function List
Item ROM
PD17003A
8K bytes (3836 x 16 bits) 320 x 4 bits
PD17005
PD17010
16K bytes (7932 x 16 bits) 432 x 4 bits 13 (+30: LCD segment pins) 41 x 4 bits 5 bits 9 bits * SIO0 clock 37.5, 75, 112.5, 225 kHz * SIO1 clock External, 37.5, 75, 450 kHz Hysteresis characteristics of SCL, SDA, SCK0, SCK1, SI0, SI1 pins
RAM Output port Control register General register pointer Stack level Serial interface
9 (+30: LCD segment pins) 33 x 4 bits 4 bits 7 bits * SIO1 clock 75, 150, 225, 450 kHz * SIO2 clock External, 75, 150, 450 kHz
D/A converter frequency Interrupt *5
878.9 Hz *6
4394.5 Hz
External : 2 (INT0 and INT1 pins) Internal : 3 (TM, SIO1, IFC)
External : 1 (INT0 pin) Internal : 4 (TM, BTM1, SIO0, IFC) External/internal: 1 (INT1 pin or timer/counter overflow)
* Interrupt priority (vector address) 1. (5H) INT0 pin 2. (4H) INT1 pin 3. (3H) Timer 4. (2H) Serial interface 1 5. (1H) Frequency counter
* Interrupt priority (vector address) 1. (6H) INT0 pin 2. (5H) INT1 pin (shared with timer/counter overflow) 3. (4H) 12-bit timer 4. (3H) Basic timer 1 5. (2H) Serial interface 0 6. (1H) Frequency counter
* System register automatic saving (4 levels) (BANK, IXE)
* System register automatic saving (3 levels) (WR, BANK, RP, PSWORD) * Address modification of IRQxxx flag
Timer
* Timer carry (Clock: 4, 10, 200, 1000 Hz) * Timer interrupt (Clock: 4, 10, 200, 1000 Hz)
* Basic timer 0 carry (Clock: 4, 10, 200, 1000 Hz) * Basic timer 1 interrupt (Clock: 4, 10, 200, 1000 Hz) * 12-bit timer (Clock: 1, 3, 90, 100 kHz)
Operational amplifier for PLL frequency synthesizer lowpass filter One-time PROM model
Provided
Not provided
PD17P005
PD17P010
417
PD17010
(2) Development Tools Item Hardware SE board Emulation probe Software Device file Macro library AS17003
PD17003A
PD17005
SE-17010 EP-17003GF AS17005
PD17010
AS17010 None
* IFCSET. LIB * IRQ. MAC
418
PD17010
(3) Notes on names of reserved words Some reserved words of the control registers of the PD17010 are different from those of the PD17003A and 17005. The following table shows the difference among the PD17010, PD17003A, and 17005 in reserved words. Item Timer
PD17003A
TMMD3 TMMD2 TMMD1 TMMD0 TMCY
PD17005
PD17010
BTM1CK1 BTM1CK0 BTM0CK1 BTM0CK0 BTM0CY TMCK3 TMCK2 TMCK1 TMCK0 TMOVF TMRPT TMRES TMEN
Item Serial interface
PD17003A
SIO2TS SIO2HIZ SIO2CK1 SIO2CK0 SIO1CH SIO1MS SIO1TX SIO1NWT SIO1WRQ1 SIO1WRQ0
PD17005
PD17010
SIO1TS SIO1HIZ SIO1CK1 SIO1CK0 SIO0CH SIO0MS SIO0TX SIO0NWT SIO0WRQ1 SIO0WRQ0 SIO0WSTT
SIO1SF8 SIO1SF9 SIO1IMD3 SIO1IMD2 SIO1IMD1 SIO1IMD0 SIO1CK3 SIO1CK2 SIO1CK1 SIO1CK0 Interrupt IPSIO1 IPTM IP1
SIO0SF8 SIO0SF9 SIO0IMD3 SIO0IMD2 SIO0IMD1 SIO0IMD0 SIO0CK3 SIO0CK2 SIO0CK1 SIO0CK0 IGRPSL IPSIO0 IPBTM1 IPGRP IPTM
PLL frequency
PLULDYL3 PLULDLY2
PLULSEN3 PLULSEN2 PLULSEN1 PLULSEN0 PLLRFCK3 PLLRFCK2 PLLRFCK1 PLLRFCK0 PWM2SEL PWM1SEL PWM0SEL CGPSEL P0YSEL P0XSEL P0ESEL P0FSEL IFCGOSTT
synthesizer PLULDLY1 PLULDLY0 PLLRFMD3 PLLRFMD2 PLLRFMD1 PLLRFMD0 D/A converter PWM2ON PWM1ON PWM0ON CGPON LCD driver P0YON P0XON P0EON P0FON IF IFCG
IRQSIO1 IRQTM
IRQSIO0 IRQBTM1 IRQTM
IRQ1
IRQGRP
419
PD17010
APPENDIX C. DEVELOPMENT TOOLS
The following tools are available to support development of the program of the PD17010.
Hardware
Name In-circuit emulator IE-17K IE-17K-ETNote 1 EMU-17KNote 2 Function IE-17K, IE-17K-ET, and EMU-17K are in-circuit emulators that can be commonly used with 17K series. IE-17K and IE-17K-ET are connected to host machine, PC-9800 series or IBM PC/ATTM, via RS-232C. EMU-17K is mounted to the expansion slot of host machine, PC-9800 series. When these in-circuit emulators are used with system evaluation board (SE board) dedicated to each model, they operate as emulators supporting that model. More sophisticated debugging environment can be created when man-machine interface software SIMPLEHOSTTM is used. EMU-17K has function to check data memory contents real-time. SE board (SE-17010) SE-17010 is SE board for PD17010 and 17P010. This board can be used alone for system evaluation or with in-circuit emulator for debugging. Emulation probe (EP-17003GF) Conversion socket (EV-9200G-80
Note 3
EP-17003GF is emulation probe for PD17010 and 17P010. When used with EV-9200G80Note 3, it connects SE board and target system. EV-9200G-80 is conversion socket for 80-pin plastic QFP (14 x 20 mm). This is used to connect EP-17003GF and target system. AF-9703, AF-9704, AF-9705, and AF-9706 are PROM programmers supporting PD17P010. When connected with programmer adapter AF-9803, they can program PD17P010.
)
PROM programmer AF-9703
Note 4
AF-9704Note 4 AF-9705Note 4 AF-9706Note 4 Program adapter (AF-9803Note 4) AF-9803 is adapter for programming PD17P010. This is used with AF-9703, AF-9704, AF-9705, or AF-9706.
Notes 1. Low-price model: external power supply type 2. Product of I.C. For details, consult I.C. 3. One EV-9200G-80 is provided to the EP-17003GF. Five EV-9200G-80s are separately available as a set. 4. These are products of Ando Electric. For details, consult Ando Electric.
420
PD17010
Software
Name 17K series assembler (AS17K) Remark AS17K is assembler that can be commonly used with 17K series. To develop program of PD17010, this assembler and device file (AS17010) are used in combination. Device file (AS17010) AS17010 is device file for PD17010 and PD17P010. This is used in combination with assembler (AS17K) for 17K series. IBM PC/AT PC DOS 5"2HC 3.5"2HC Support software (SIMPLEHOST) PC-9800 series MS-DOS IBM PC/AT PC DOSTM Host Machine PC-9800 series OS MS-DOSTM Distribution Media 5"2HD 3.5"2HD 5"2HC 3.5"2HC 5"2HD 3.5"2HD Order Code
S5A10AS17K S5A13AS17K S7B10AS17K S7B13AS17K
S5A10AS17010 S5A13AS17010 S7B10AS17010 S7B13AS17010
SIMPLEHOST is man-machine interface software that runs on WindowsTM when program is developed by using in-circuit emulator and personal computer.
PC-9800 series MS-DOS Windows IBM PC/AT PC DOS
5"2HD 3.5"2HD 5"2HC 3.5"2HC
S5A10IE17K S5A13IE17K S7B10IE17K S7B13IE17K
Remark The version of the supported OS is as follows:
OS MS-DOS PC DOS Windows Version Ver. 3.30 to Ver. 5.00ANote Ver. 3.1 to Ver. 5.0Note Ver. 3.0 to Ver. 3.1
Note
Although MS-DOS Ver. 5.00/5.00A and PC DOS Ver.5.0 have a task swap function, this function cannot be used with this software.
421
PD17010
[MEMO]
422
PD17010
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
Purchase of NEC I2C components conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
423
PD17010
SIMPLHOST is a trademark of NEC Corporation.
MS-DOS and Windows are trademarks of Microsoft Corporation. PC/AT and PC DOS are trademarks of IBM Corporation.
The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or reexport of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative.
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customer must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices in "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact NEC Sales Representative in advance. Anti-radioactive design is not implemented in this product.
M4 94.11
424

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